Use Cases

Automatic ECO

• From Hours to Minutes — stop re-running full ECO on every netlist stage
• Automatic Functional ECO By Reference Netlist
• RTL Guided Without Re-Synthesis
• Functional ECO in a 2 Million Gate Design
• Navigating Post-Layout ECO: Challenges and Solutions with GOF ECO
• Bridging the Gap: Effortless EDA Scripting Through Natural Language and AI
• Streamlining IC ECO with Intelligent Script Application in GOF ECO
• Different Types of ECO
• GOF ECO: Leading the Way in Combinational Logic ECO
• Synthesize sub-modules to create top Reference Netlist incrementally
• Automatic Standard Cell Metal Only ECO
• Metal Only ECO by Borrowed Logic Cone
• Test mode constraints in functional netlist ECO
• Multi-Step LEC
• Pinpoint missing DFT constraint by counter example debug
• RTL Guided Functional ECO Flow
• RTL Patch ECO
• Insert RTL into netlist to perform fast ECO
• ECO Retargeting
• Automatic Functional ECO, Partial Mode
• Reset Set flop swapping netlist ECO
• Spare Gates Mapping in Metal Only ECO
• Constraint on Spare Gates Type and Number
• Metal Configurable Gate Array Spare Cells ECO
• DFT Constraints for Automatic Functional ECO and LEC
• Flip-flop Phase Inverted
• Multibit flops in ECO
• Why does multibit flop gate-to-gate comparison fail in Formality?
• No Exact Pin Match
• Mixed Automatic and Manual ECO
• Clock Gating or MUX
• Reduce ECO Fix Scope
• Optimal ECO Strategy: Lockup Latches Handling in Automatic ECO
• Automatic Datapath ECO
• Convert Spare Gate Types
• Automatic DFT ECO

AI Agentic Flow in GOF Platform

• GOF AI Skill — drive netlist ECO from your agentic CLI (Claude Code, Codex, opencode)
• AI is Surpassing Human Manual ECO
• AI-Driven Power Flow Compliance Checking
• Multi-Trial LLM ECO with 60% Performance Boost
• AI Agents + RTL Guided ECO
• Beyond Logic: AI-Driven Automation for DFT-Aware Functional ECO
• Non-equivalent points debug automation by AI Agent
• Streamlining Netlist ECO with AI-Powered Image Processing
• VSCode AI Integration for ECO
• AI-Powered Natural Language ECO
• Minimizing Netlist Patch Size in RTL ECO with GOF AI
• RTL to RTL LEC for AI generated Verilog RTL
• AI-Driven ECO: From Natural Language to Automated Complex Operations
• Multi-stages ECO: From Hours to Minutes with GOF's Single Script Approach
• RTL to RTL ECO with AI Agent
• Streamlining ECO Function Calls with a Unified LLM API
• AI in ECO decisions
• Automatic Functional netlist ECO By Gemini and Copilot

Functional Safety

• GOF Formal Introduction
• GOF Formal Example Codes
• Fault Propagation Debug by VCD and Schematic
• TMR ECO in functional safety

DFT Friendly ECO

• DFT-aware ECO with GOF: preserve scan integrity through functional changes
• DFT Design Rule Checker
• DFT DRC script from AI tech support
• DFT friendly functional netlist ECO
• Stitch new flops into scan chains in ECO
• Pick the right signal for DFT in ECO
• Insert lockup cells to scan output ports
• Insert masking gates to analog outputs
• Reset Set flop swapping netlist ECO

GOF Beats Conformal

• GOF vs Conformal ECO — side-by-side comparison & displacement guide
• DCT/DCG netlist ECO
• GOF vs Conformal ECO
• Combinational logic ECO
• DFT friendly ECO
• Reset Set flop swapping netlist ECO

Script Mode Manually ECO

• TMR ECO in functional safety
• Swap instances to improve routing quality and timing
• Script Mode Manually Metal Only ECO
• Script Mode Modify State Machine and Debug
• Insert Isolation Gates in Low Power Design
• Issues faced in Manual ECO

GUI Mode ECO

• GUI Mode Netlist Debug
• GUI Mode ECO Dynamic Demo
• Modify 3 bits state machine in GUI ECO
• Add reverse edge Flip-Flops
• Insert inverters (PDF)
• Add a hierarchical module (PDF)
• GUI mode metal only ECO, one spare gate is added

Gate Level Simulation Flow

• Gate level simulation (GLS) flow
• Remove 'x' in gate level simulation
• Gate level boundary optimization debug

Netlist Debug/Report

• Non-equivalent points debug automation by AI Agent
• Non-equivalence debug on counterexample on Schematic
• Natural Language Debugging in GOF Shell
• Hierarchical Debug In Non-Equivalence Checking
• Set/reset race condition fix by ECO
• Retiming and LEC
• Find equal nets in Implementation Netlist For Reference RTL wire
• Net names collision in Verilog to Spice conversion
• Clock tree fast trace
• Debug non-equivalent points
• Design Statistic
• Graphic mode vs Text mode
• Calculate clock gating percentage
• Debug Connectivity (PDF)
• Flexible Schematic generator
• Script Mode Modify State Machine and Debug
• Layout Placement Regions View
• Circuit Placement View on Layout