A Practical Way to Do Netlist ECO & Debug

Modify three register bits in GUI mode

Abstract

This use case demonstrates how to modify 3 bits state machine with MUX gates. The new logic requires state machine change to 3'b001 when current state is 3'b111. 3'b111 -> 3'b001.

ECO by modification on Schematic

The first step is to load the state machine flops on the schematic. Several ways to launch schematic and load gates. One way is to double click the gate instance, the schematic window will pop up with the gate on it.

Use menu File->'Load Gate' and enter the other instances need to be loaded.

After three state machine flops are loaded, click Mouse-Middle-Button on D input pins of these flops to get flops'D fanins.

Check 'ECO' checkbutton to enable ECO mode. ECO buttons become active. Select three D input lines for further ECO operations.

Click ECO button "insert gates into connections"

A pop window is asking for the number of gates to be inserted in each line. The number is '1' in this case. Since only one MUX is needed in each D input line. Click Ok.

"Select ECO Gate to insert" window pops up for gate type selection. Type "mx" in Filter Entry to filter out gate name having string "mx" (Case ignored).  Click OK button.

"Select ECO cell pins Connectivities" window pops up for pin connections pre-selection. 'Complete Loop' means connecting up the line the gate inserting in. So 'Y' will drive the line destination, 'A' will accept the line source input. Leave "B" and "S0" with option "Undriven" for later connections. Click OK button.

The three MUXs are inserted in the three lines and three new nets are created which are driven by output s of new ECO added MUXs.

The next thing is to create current state 3'b111, which is done by 3 inputs AND. Click 'Add gate' ECO button to add 'AND3X4'

Press Mouse-middle-button on input pins of 'AND3X4', don't release the button, move the cursor to the flops outputs. Check "Connect Cells" feature for detail.

Move the 'AND3X4' gate to close to 3 MUXs.

Use same way to connect 'S0' of the 3 MUXs to output of 'AND3X4'.

Click 'Add gate' ECO button to pick "1'b0" and "1'b1". In 'Add ECO gate' window, press 'Ctrl', click mouse on the gate name to select multiple gates. (Constant 0 and 1 are selected at the same time in this case). Click OK button.

Connect 1'b1 to 'B' pin of the first MUX, and 1'b0 to 'B' pins of the other two MUXs. Same way as used in connecting 'AND3X4' gate.

Don't forget to save schematic from time to time to avoid losing data.

At the end, click "Save ECO result to file" button.

The result can be in multiple formats. Verilog and tcl are recommended to use. All the other formats may need manually edited. Tcl format result is attached below.

#ECO012345 Primetime TCL format

current_design TM_qciflt
disconnect_net [get_nets N278] [get_pins qcifvnumber_reg_0_/D]
disconnect_net [get_nets N280] [get_pins qcifvnumber_reg_2_/D]
disconnect_net [get_nets N279] [get_pins qcifvnumber_reg_1_/D]
create_net eco012345_N279_0
create_net eco012345_ECONET_3_Y
create_net eco012345_N280_1
create_net eco012345_N278_2
create_cell eco012345_ECOCELL_0 90nm_hv.synth/MX2X4
if {{} == [get_cells Logic1]} {
create_cell -logic 1 Logic1
create_net *Logic1*
connect_net *Logic1* Logic1/**logic_1**
}
create_cell eco012345_ECOCELL_3 90nm_hv.synth/AND3X4
if {{} == [get_cells Logic0]} {
create_cell -logic 0 Logic0
create_net *Logic0*
connect_net *Logic0* Logic0/**logic_0**
}
create_cell eco012345_ECOCELL_1 90nm_hv.synth/MX2X4
create_cell eco012345_ECOCELL_2 90nm_hv.synth/MX2X4
connect_net [get_nets eco012345_ECONET_3_Y] [get_pins eco012345_ECOCELL_0/S0]
connect_net [get_nets N279] [get_pins eco012345_ECOCELL_0/A]
connect_net [get_nets eco012345_N279_0] [get_pins eco012345_ECOCELL_0/Y]
connect_net [get_nets [all_connected "Logic0/**logic_0**" ]] [get_pins eco012345_ECOCELL_0/B]
connect_net [get_nets eco012345_N278_2] [get_pins qcifvnumber_reg_0_/D]
connect_net [get_nets mqcifvnumber[2]] [get_pins eco012345_ECOCELL_3/C]
connect_net [get_nets mqcifvnumber[0]] [get_pins eco012345_ECOCELL_3/A]
connect_net [get_nets eco012345_ECONET_3_Y] [get_pins eco012345_ECOCELL_3/Y]
connect_net [get_nets mqcifvnumber[1]] [get_pins eco012345_ECOCELL_3/B]
connect_net [get_nets eco012345_ECONET_3_Y] [get_pins eco012345_ECOCELL_1/S0]
connect_net [get_nets N280] [get_pins eco012345_ECOCELL_1/A]
connect_net [get_nets eco012345_N280_1] [get_pins eco012345_ECOCELL_1/Y]
connect_net [get_nets [all_connected "Logic0/**logic_0**" ]] [get_pins eco012345_ECOCELL_1/B]
connect_net [get_nets eco012345_N280_1] [get_pins qcifvnumber_reg_2_/D]
connect_net [get_nets eco012345_N279_0] [get_pins qcifvnumber_reg_1_/D]
connect_net [get_nets eco012345_ECONET_3_Y] [get_pins eco012345_ECOCELL_2/S0]
connect_net [get_nets N278] [get_pins eco012345_ECOCELL_2/A]
connect_net [get_nets eco012345_N278_2] [get_pins eco012345_ECOCELL_2/Y]
connect_net [get_nets [all_connected "Logic1/**logic_1**" ]] [get_pins eco012345_ECOCELL_2/B]

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