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Home
Products
GOF ECO
GOF Formal
GOF LEC
GOF Debug
Support
Download GOF
Request License
Documents
GOF User Manuals
GOF Script APIs
GOF Run Command
Use Cases
Video Demos
About
About Us
Contact Us
What People Say
Release History
Use Cases
Automatic ECO
Automatic Functional ECO By Reference Netlist
Automatic Standard Cell Metal Only ECO
Metal Only ECO by Borrowed Logic Cone
RTL Guided Functional ECO Flow
RTL Patch ECO
Insert RTL into netlist to perform fast ECO
ECO Retargeting
Automatic Functional ECO, Partial Mode
Reset Set flop swapping netlist ECO
Spare Gates Mapping in Metal Only ECO
Constraint on Spare Gates Type and Number
Metal Configurable Gate Array Spare Cells ECO
DFT Constraints for Automatic Functional ECO and LEC
Flip-flop Phase Inverted
Multibit flops in ECO
No Exact Pin Match
Mixed Automatic and Manual ECO
Clock Gating or MUX
Reduce ECO Fix Scope
Lockup Latches Handling in Automatic ECO
Automatic Datapath ECO
Convert Spare Gate Types
Automatic DFT ECO
Functional Safety
GOF Formal Introduction
GOF Formal Example Codes
Fault Propagation Debug by VCD and Schematic
TMR ECO in functional safety
DFT Friendly ECO
DFT Design Rule Checker
DFT friendly functional netlist ECO
Stitch new flops into scan chains in ECO
Pick the right signal for DFT in ECO
Insert lockup cells to scan output ports
Insert masking gates to analog outputs
Reset Set flop swapping netlist ECO
GOF Beats Conformal
DCT/DCG netlist ECO
GOF vs Conformal ECO
GOF Beats Conformal ECO Case 1
GOF Beats Conformal ECO Case 2
GOF Beats Conformal ECO Case 3 (Mixed Mode)
GOF Beats Conformal ECO case 4 (Two Steps)
Reset Set flop swapping netlist ECO
Script Mode Manually ECO
TMR ECO in functional safety
Swap instances to improve routing quality and timing
Script Mode Manually Metal Only ECO
Script Mode Modify State Machine and Debug
Insert Isolation Gates in Low Power Design
GUI Mode ECO
GUI Mode Netlist Debug
GUI Mode ECO Dynamic Demo
Modify 3 bits state machine in GUI ECO
Add reverse edge Flip-Flops
Insert inverters (PDF)
Add a hierarchical module (PDF)
GUI mode metal only ECO, one spare gate is added
Gate Level Simulation Flow
Gate level simulation (GLS) flow
Remove 'x' in gate level simulation
Gate level boundary optimization debug
Netlist Debug/Report
Non-equivalence debug on counterexample on Schematic
Find equal nets in Implementation Netlist For Reference RTL wire
Net names collision in Verilog to Spice conversion
Clock tree fast trace
Debug non-equivalent points
Design Statistic
Graphic mode vs Text mode
Calculate clock gating percentage
Debug Connectivity (PDF)
Flexible Schematic generator
Script Mode Modify State Machine and Debug
Layout Placement Regions View
Circuit Placement View on Layout
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