Automatic DFT ECO Flow

Overview

In functional netlist ECO, DFT logic is disabled by setting constraints. But to fix DFT logic in automatic netlist ECO, the constraints should be removed. The DFT logic in Reference Netlist is used to guide how to fix Implementation Netlist. However, the DFT automatic ECO flow only targets those DFT logic with fixed naming style. Some DFT tools may add random naming style flops in implementing DFT feature, for example, IEEE1500 wrapper cell feature. In those complicated DFT designs, users may still rely on manual ECOs for the DFT logic changes.

DFT ECO Process

The DFT scripts are updated to add the new features which can be adding a new TDR register for example. The DFT tool is run to insert the new DFT logic into the design and the new netlist including DFT logic is saved as Reference Netlist.

Reference Netlist is read in GOF ECO script to fix Implementation Netlist.

The detail script for DFT automatic ECO:

# GOF ECO script, run_dft_auto.pl
use strict;
undo_eco; # Discard previous ECO operations
setup_eco("eco_dft_auto");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
read_design("-ref", "dft_new_ref.gv");# Read in Reference Netlist with new DFT
read_design("-imp", "postnetlist_old_dft.gv");# Read in Implementation Netlist Which is under ECO
set_top("top_wrapper");# Set the top module
fix_design;
report_eco(); # ECO report
write_verilog("imp_dft_eco.gv");# Write out ECO result in Verilog
exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

The following figure shows the DFT logic having one TDR register added. Four new instances are added in the ECO

Figure 1: Automatic DFT ECO


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