GOF LEC is the logic equivalence checker tool in GOF platform. It doesn't need the synthesis help information like SVF file. The two designs in comparison can be in RTL or Netlist format. RTL format supports SystemVerilog2017. The read design method is different in supporting RTL and Netlist.
Figure 1: GOF LEC Engine
The following is the example script for RTL to Netlist LEC:
# LEC script, run_rtl2net_lec.pl use strict; read_library("art.5nm.lib"); # Read in standard library set_inc_dirs("-ref", "inc_dir_path/include"); set_define("-ref", "NO_SIMULATION", 1); my @rtl_files = ("cpu_core.sv", "mem_ctrl.sv", "display_sys.sv", "chip_top.sv"); read_rtl("-ref", @rtl_files); # Read in the Reference RTL files read_design('-imp', 'chip_top.v'); # Read in the Synthesis Netlist set_top("CHIP_TOP"); # Set the top module set_ignore_output("scan_out*"); set_pin_constant("scan_enable", 0); set_pin_constant("scan_mode", 0); elab_rtl(); # RTL processing my $non_equal = run_lec; # Run logic equivalence checking on RTL vs Netlist if($non_equal){ gprint("LEC failed with $non_equal non-equivalent points"); }else{ gprint("LEC passed"); }
The following is the example script for Netlist to Netlist LEC:
# LEC script, run_net2net_lec.pl use strict; read_library("art.5nm.lib"); # Read in standard library read_design('-ref', 'AI2021_top_syn.v'); # Read in the Reference Netlist, prelayout netlist read_design('-imp', 'AI2021_top_pr.v'); # Read in the Implementation Netlist, postlayout netlist set_top("AI2021_top"); # Set the top module set_ignore_output("scan_out*"); set_pin_constant("scan_enable", 0); set_pin_constant("scan_mode", 0); my $non_equal = run_lec; # Run logic equivalence check on the two netlists if($non_equal){ gprint("LEC failed with $non_equal non-equivalent points"); }else{ gprint("LEC passed"); }
