A Practical Way to Do Netlist ECO & Debug

GOF Netlist ECO User Manual V1.9

  1. 1 Introduction
    1. 1.1 Overview
    2. 1.2 Netlist ECO Solutions
    3. 1.3 Download and Install GOF
    4. 1.4 License and Setup
  2. 2 Netlist ECO Flows
    1. 2.1 Automatic Full-Layers ECO Flow
      1. 2.1.1 Overview
      2. 2.1.2 Files and data requirements
      3. 2.1.3 Steps to do automatic functional ECO
      4. 2.1.4 Automatic Functional ECO example script
      5. 2.1.5 Run and debug
      6. 2.1.6 Partial Mode
      7. 2.1.7 Incremental Mode
      8. 2.1.8 Exclude Test Logic
      9. 2.1.9 No Exact Pin Match
      10. 2.1.10 Flip-flop Phase Inverted
      11. 2.1.11 Cutpoint Method Enable
      12. 2.1.12 Dedicated Logic Equivalence Check Engine
      13. 2.1.13 Stitch new flops into scan chain
      14. 2.1.14 Add a new module
      15. 2.1.15 Note in RTL modification and re-synthesis
        1. 2.1.15.1 Keep sequential signal name
        2. 2.1.15.2 Use the same synthesis constraints
      16. 2.1.16 Check design after ECO
    2. 2.2 Automatic Metal Only ECO Flow
      1. 2.2.1 Overview
      2. 2.2.2 Files and data requirements
      3. 2.2.3 Steps to do automatic Metal Only ECO
      4. 2.2.4 Example GofCall script for Metal Only ECO
      5. 2.2.5 Run and debug
      6. 2.2.6 Gated clocks in AutomaticMetal Only ECO
    3. 2.3 Script Mode Full Layers Manual ECO Flow
      1. 2.3.1 Overview
      2. 2.3.2 Steps to do Manual ECO In Scripts
      3. 2.3.3 Locate ECO point
      4. 2.3.4 Files and data requirements
      5. 2.3.5 ECO APIs list
      6. 2.3.6 Example GofCall script for Manual ECO
      7. 2.3.7 Run and debug
      8. 2.3.8 Handle repetitive work
      9. 2.3.9 Special character
    4. 2.4 Script Mode Metal Only Manual ECO Flow
      1. 2.4.1 Overview
      2. 2.4.2 Files and data requirements
      3. 2.4.3 Example GofCall script for Manual Metal Only ECO
      4. 2.4.4 Run and debug
    5. 2.5 GUI Mode Full Layers ECO Flow
      1. 2.5.1 Overview
      2. 2.5.2 Start up GOF in GUI Mode
      3. 2.5.3 Create Partial Schematic
      4. 2.5.4 Do ECO on schematic
      5. 2.5.5 Save ECO
    6. 2.6 GUI Mode Metal Only ECO Flow
      1. 2.6.1 Overview
      2. 2.6.2 Methods for Metal Only ECO
      3. 2.6.3 Setup and use cases
  3. 3 Script Mode Detail Features
    1. 3.1 GofCall Script
      1. 3.1.1 Get Help
      2. 3.1.2 Feature list
      3. 3.1.3 API list
      4. 3.1.4 API grouping
        1. 3.1.4.1 Netlist Browse APIs
        2. 3.1.4.2 Automatic ECO APIs
        3. 3.1.4.3 File IO APIs
        4. 3.1.4.4 Manual ECO APIs
      5. 3.1.5 API usage
    2. 3.2 String Handling In Script Mode
      1. 3.2.1 Single quote and double quote
      2. 3.2.2 Instance and net with backslash
    3. 3.3 Run and debug GofCall script
      1. 3.3.1 Command line
      2. 3.3.2 GOF Shell
      3. 3.3.3 Run in GUI mode
      4. 3.3.4 Fast schematic launch
      5. 3.3.5 Break points for debug
    4. 3.4 Typical Manual ECO operations
      1. 3.4.1 Insert gate to port
        1. 3.4.1.1 Insert an invert to input port
        2. 3.4.1.2 Insert to output port
        3. 3.4.1.3 Insert inverts to multiple ports
      2. 3.4.2 Insert gate to register instance pin
        1. 3.4.2.1 Insert invert to flop data pin
        2. 3.4.2.2 Insert invert to flop output pin
        3. 3.4.2.3 Insert MUX to data pin of multiple flops
      3. 3.4.3 Change flops to other type
        1. 3.4.3.1 Change non-reset flop type to resettable flop
      4. 3.4.4 Insert gate to hierarchical instance pin
        1. 3.4.4.1 Insert invertsto hierarchical instance pins
        2. 3.4.4.2 Insert AND to hierarchical instance pins
  4. 4 GUI Mode Detail Features
    1. 4.1 GofViewer
      1. 4.1.1 Log Window
      2. 4.1.2 File Menu
        1. 4.1.2.1 Load Design
        2. 4.1.2.2 Reload Design
        3. 4.1.2.3 Open Other Netlist
        4. 4.1.2.4 Open Log Window
        5. 4.1.2.5 Exit
      3. 4.1.3 Find Menu
        1. 4.1.3.1 Search
        2. 4.1.3.2 Goto Line Number
        3. 4.1.3.3 Report Area
        4. 4.1.3.4 Report Leakage
        5. 4.1.3.5 Report Leaf Cells
        6. 4.1.3.6 Report Submodules
        7. 4.1.3.7 Statistic of Current Design
        8. 4.1.3.8 List Library
        9. 4.1.3.9 List Context for Leaf Cell
      4. 4.1.4 Commands Menu
        1. 4.1.4.1 Launch GofTrace Schematic
        2. 4.1.4.2 Launch GofTrace with Gate
        3. 4.1.4.3 Launch Layout Viewer
        4. 4.1.4.4 Launch GofCall Script Interface
        5. 4.1.4.5 Switch to GOF Shell Mode
        6. 4.1.4.6 Spare Cells
        7. 4.1.4.7 Launch Files Compare Window
        8. 4.1.4.8 Process Timing Violations
        9. 4.1.4.9 SDF
      5. 4.1.5 Options Menu
        1. 4.1.5.1 Hierarchy Window Font
        2. 4.1.5.2 Netlist Window Font
        3. 4.1.5.3 Dump Waveform Restore File
        4. 4.1.5.4 Setup
      6. 4.1.6 Help Menu
        1. 4.1.6.1 General
        2. 4.1.6.2 About
        3. 4.1.6.3 nandigits.com/gof_manual.php
        4. 4.1.6.4 Read Ethernet Mac Address
      7. 4.1.7 Keyboard Shortcuts
        1. 4.1.7.1 Access Menu
        2. 4.1.7.2 Functions access
      8. 4.1.8 Selection Status
      9. 4.1.9 Netlist Window Pop Menu
        1. 4.1.9.1 Search
        2. 4.1.9.2 Copy Selected to
        3. 4.1.9.3 Driver of the selected net
        4. 4.1.9.4 List Connectivity of the selected net
        5. 4.1.9.5 List Fanin EndPoints
        6. 4.1.9.6 List Fanout EndPoints
        7. 4.1.9.7 Parent Module
        8. 4.1.9.8 List Context
      10. 4.1.10 Hierarchy Window Pop Menu
        1. 4.1.10.1 Show Definition
        2. 4.1.10.2 Show Calling
        3. 4.1.10.3 Report Area of the selected design
        4. 4.1.10.4 Report Leakage of the selected design
        5. 4.1.10.5 Report Leaf Cells of the selected design
        6. 4.1.10.6 Report Submodules of the selected design
        7. 4.1.10.7 Statistic of the selected design
        8. 4.1.10.8 Edit Module of the selected design
        9. 4.1.10.9 Save Module of the selected design
        10. 4.1.10.10 Goto Line Number
    2. 4.2 GofTrace
      1. 4.2.1 Mouse buttons usage
        1. 4.2.1.1 Mouse Left Button
        2. 4.2.1.2 Mouse Middle Button
        3. 4.2.1.3 Mouse Right Button
      2. 4.2.2 File Menu
        1. 4.2.2.1 Save
        2. 4.2.2.2 Open
        3. 4.2.2.3 Print
        4. 4.2.2.4 Exit
      3. 4.2.3 Schematic Menu
        1. 4.2.3.1 New Schematic
        2. 4.2.3.2 List Gate
        3. 4.2.3.3 Load Gate
        4. 4.2.3.4 Load Gate Driving Net
        5. 4.2.3.5 List Selected Instances
        6. 4.2.3.6 List Selected Wires
        7. 4.2.3.7 List Selected Modules
        8. 4.2.3.8 List Selected Instances Definitions
        9. 4.2.3.9 List Selected Gates Types
        10. 4.2.3.10 Zoom In
        11. 4.2.3.11 Zoom Out
        12. 4.2.3.12 Zoom to
        13. 4.2.3.13 Find Gates on Schematic
        14. 4.2.3.14 Find Nets on Schematic
        15. 4.2.3.15 Undo Schematic Operations
        16. 4.2.3.16 Place and Route
        17. 4.2.3.17 Create PS/PDF File
      4. 4.2.4 Commands Menu
        1. 4.2.4.1 View Gates in Layout
        2. 4.2.4.2 Load Layout Files
        3. 4.2.4.3 Launch GofCall Script Interface
        4. 4.2.4.4 Spare Cells
        5. 4.2.4.5 Launch Files Compare Window
        6. 4.2.4.6 Process Timing Violations
        7. 4.2.4.7 SDF
      5. 4.2.5 Options Menu
        1. 4.2.5.1 Increase Font Size
        2. 4.2.5.2 Decrease Font Size
        3. 4.2.5.3 Show Port
        4. 4.2.5.4 Show Wire
        5. 4.2.5.5 Show Title
        6. 4.2.5.6 Show Type
        7. 4.2.5.7 Show Connections
        8. 4.2.5.8 Show Comment
        9. 4.2.5.9 Dump Waveform Restore File
        10. 4.2.5.10 Save String to Clipboard
        11. 4.2.5.11 Cursor Mode
        12. 4.2.5.12 Line Edit Mode
        13. 4.2.5.13 Setup
      6. 4.2.6 Help Menu
        1. 4.2.6.1 General
        2. 4.2.6.2 About
        3. 4.2.6.3 nandigits.com/gof_manual.php
      7. 4.2.7 Keyboard Shortcuts
        1. 4.2.7.1 Access Menu
        2. 4.2.7.2 Functions access
      8. 4.2.8 Selection Status
      9. 4.2.9 GofTrace Pop Menu
        1. 4.2.9.1 Driver Until Non Buffer
        2. 4.2.9.2 Drivers of Logic Cone
        3. 4.2.9.3 Copy Selected to
        4. 4.2.9.4 Nets Equivalence Check
        5. 4.2.9.5 Find Logic Equivalent Nets
        6. 4.2.9.6 Find Circuit between Two Points
        7. 4.2.9.7 Add Comments
        8. 4.2.9.8 Find Gates on Schematic
        9. 4.2.9.9 Find Nets on Schematic
        10. 4.2.9.10 Place and Route
        11. 4.2.9.11 Find selected in GofViewer
        12. 4.2.9.12 Edit Gate Display
        13. 4.2.9.13 List Logic for the Selected Leaf Cell
        14. 4.2.9.14 List Context for the Selected Leaf Cell
        15. 4.2.9.15 List Definition for the Selected Instance
        16. 4.2.9.16 Load Instance Similar to the Selected Instance
        17. 4.2.9.17 Equivalent Symbol
        18. 4.2.9.18 Delete
    3. 4.3 GofECO
      1. 4.3.1 ECO Menu
        1. 4.3.1.1 Enable ECO and ECO Preferences
        2. 4.3.1.2 Insert Gates
        3. 4.3.1.3 Replace Gates
        4. 4.3.1.4 Add Gates
        5. 4.3.1.5 Delete Selected Items
        6. 4.3.1.6 Upsize Drive Strength
        7. 4.3.1.7 Downsize Drive Strength
        8. 4.3.1.8 Undo ECO Operations
        9. 4.3.1.9 Add Connection
        10. 4.3.1.10 Save ECO
      2. 4.3.2 Metal Only ECO
        1. 4.3.2.1 Metal ECO, mode 1
        2. 4.3.2.2 Metal ECO, mode 2
        3. 4.3.2.3 Metal ECO, mode 3
        4. 4.3.2.4 Metal ECO, mode 4
    4. 4.4 LayoutViewer
      1. 4.4.1 File Menu
        1. 4.4.1.1 Capture in PDF
        2. 4.4.1.2 Exit
      2. 4.4.2 Commands Menu
        1. 4.4.2.1 Clear Circuit Markers
        2. 4.4.2.2 Clear Search Markers
        3. 4.4.2.3 New Schematic
      3. 4.4.3 OptionsMenu
        1. 4.4.3.1 Show Grid
        2. 4.4.3.2 Show Instance
        3. 4.4.3.3 Show Module
        4. 4.4.3.4 Setup
      4. 4.4.4 Help Menu
        1. 4.4.4.1 Help on LayoutViewer
      5. 4.4.5 LayoutViewer Pop Menu
        1. 4.4.5.1 Clear Circuit Markers
        2. 4.4.5.2 Clear Searching Markers
        3. 4.4.5.3 Copy Selected to
      6. 4.4.6 Keyboard and mouse combination
        1. 4.4.6.1 Ctrl key to measure length
        2. 4.4.6.2 Shift key to select multiple markers
      7. 4.4.7 Mouse operations
      8. 4.4.8 Select color buttons
      9. 4.4.9 Search function
  5. 5 Appendix A
    1. 5.1 GOF Command Options
    2. 5.2 Command line Examples
  6. 6 Appendix B
    1. 6.1 Fatal codes
    2. 6.2 Error codes
    3. 6.3 Warning codes
    4. 6.4 GUI warning codes

1 Introduction

 

1.1 Overview

GOF, Gates On the Fly, provides complete netlist solutions to accommodate various netlist ECO and debug scenarios.

  • Complete Netlist ECO solutions
  • Fully Interactive Schematic
  • Netlist Lint Checker
  • Flexible Netlist Database Report
  • Script Interface for Tool Extensions
  • Parallel Processing on Multi-core Host

1.2 Netlist ECO Solutions

 

Gates On the Fly implements several cutting edge ECO methodologies. Netlist ECO varies in size and complexity from case to case. Design process changes from company to company. Gates On the Fly gives users flexibility to choose one or several of the methodologies depending on the size and complexity of the changes.

  • Automatic ECO and Manual ECO
  • Script Mode and GUI Mode
  • Metal Only ECO and All Layers ECO

 

  • Automatic mode ECO

The automatic functional ECO is done by a GofCall ECO script. The flow needs Implementation Netlist which is under ECO, and Reference Netlist which is re-synthesized from modified RTL with the same constraints as the pre-layout netlist. The top down API 'fix_design' is used to perform a global ECO. GOF uses the built-in Logic Equivalence Check engine to find and analyze the non-equivalent points in the top level module and its sub-modules. Logic patches are created to fix the non-equivalent modules. The final patches are optimized circuits with minimum gate count that make Implementation Netlist equal to Reference Netlist. The patches can be mapped to spare-type-gates by 'map_spare_cells' API.

  • Manual mode ECO

When ECO changes are known and ECO size is small or the operations are repetitive like adding inverts on a bus, manual mode ECO is a better choice. Since it is more efficient and the final gates touched can be less than automatic mode ECO. Moreover, automatic and manual mode ECO can be interleaved in one GofCall ECO script.

  • Metal Only ECO

When ECO is done in either automatic mode or manual mode, 'map_spare_cells' command is run to convert the newly added cells to spare gate types cells. Users can control only spare gate type cells being used in manual mode ECO, so that the converting stage can be bypassed.

  • Hierarchical ECO

GOF supports hierarchical ECO by set the ECO scope to the sub-modules. Some Logic Equivalence Check cases can only be resolved in flatten mode. Since GOF only focuses on the modules or spots that user specifies, it can avoid to fall into the trap of LEC failing in hierarchical netlist.

  • GUI mode ECO

GUI mode ECO has advantage of fast ramping up. It’s good for small size ECOs. The incremental schematic feature is very helpful for analyzing the netlist before the next step is decided.

  • Integrated environment

The incremental schematic is very useful in pinpointing the logic issues. GOF supports many useful APIs to fast access the database.

In section 2, eight ECO flows are listed to accommodate different ECO scenarios. In section 3, a guideline is provided for choosing the ECO flow.

1.3 Download and Install GOF

GOF release package can be found in

https://nandigits.com/download.php?gvt=0

The tool supports Linux 64bits OS. Download the release package and unzip to a directory. Set 'the_64bit_install_path/GOF64/bin' in search path.

1.4 License and Setup

Contact support@nandigits.com for evaluation license, if the evaluation netlist size is larger than 500K bytes. There are two license modes, fixed node mode and floating node mode.

2 Netlist ECO Flows

2.1 Automatic Full-Layers ECO Flow

2.1.1 Overview

Full layers functional ECO can add or delete gates freely. The ECO operations are done in a GofCall script which is compatible with Perl, and it uses exported APIs to access the netlist database. GOF reads in two netlist files, Implementation Netlist which is under ECO and Reference Netlist which is re-synthesized from modified RTL with the same constraints as the pre-layout netlist. In the GofCall script, the top down API 'fix_design' is used to fix the top level module and its sub-modules in global mode. GOF uses the built-in Logic Equivalent Check Engine to figure out the non-equivalent points. And optimized minimum size gate patches are applied to fix the non-equivalent modules.

As shown in Figure 1, two logic cones are extracted from the implementation and reference netlist for the same compare point. The implementation point mismatches the reference point initially. GOF compares the two points and generated a patch from Reference logic cone and applies to Implementation Netlist. After the patching, the two points become equivalent.

 

 

Figure 1: Logic Cone Optimization

GOF does logic cone analysis and optimization for each failing point found in top down logic equivalence check. The failing point is in format of output port or sequential element’s input pin, such as flop’s D input. The final patch has the minimum number of gates to make the implementation logic cone equal to the reference logic cone.

The flow chart is shown in Figure 2.

 

Figure 2: Automatic functional ECO flow

2.1.2 Files and data requirements

  • Standard library (Synopsys Liberty) files with extension '.lib'
  • Other Verilog libraries files if not covered in '.lib' files
  • Implementation Netlist on which ECO is done
  • Reference Netlist synthesized with the same constraints as the pre-layout netlist
  • The level module name under ECO

 

2.1.3 Steps to do automatic functional ECO

A typical situation for an automatic functional ECO:

  • Modify RTL
  • Synthesize the new RTL to get Reference Netlist
  • Create a GofCall ECO script:
    • Specify ECO name in 'setup_eco'
    • Load Standard Cell libraries and Verilog libraries
    • Load Reference Netlist and Implementation Netlist
    • Add fix command 'fix_design'
    • Report ECO status and write out ECO results
  • Run the above script

2.1.4 Automatic Functional ECO example script

The GofCall script has exact the same syntax of Perl script. It can execute exported APIs that access the netlist database and modify the netlist.

The following is an example script for an automatic functional ECO:

# GofCall ECO script, run_example.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.5 Run and debug

The GofCall Script can be run by ‘-run’ option.

gof -run run_example.pl

Check Run and debug GofCall script section for more detail

2.1.6 Partial Mode

If all RTL changes are known to be contained in one sub-block and its sub-modules, the top level scope can be set to the sub-block. 'fix_design' can apply to the block and its sub-modules.

 

Figure 3: Partial Mode

For example, the above design has only MPU/HBUS/MEM modified. The top level can be set to MPU by 'set_top("MPU")'

# GofCall ECO script, run_example_partial.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("MPU");# Set the top module to MPU instead of the most top module SOC_TOP
fix_design;
set_top("SOC_TOP"); # Set the top module to the most top module
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.7 Incremental Mode

User can choose to fix the selected modules in implementation netlist, when RTL changes are known to be isolated inside the specified modules.

 

Figure 4: Incremental Mode

For example, the above design has only two modules modified, WIFI and ENC, and the changes are isolated in these two modules not propagating through hierarchical ports.

ECO API, 'fix_modules' can be run on these two modules.

# GofCall ECO script, run_example_incremental.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
fix_modules("WIFI", "ENC");
set_top("SOC_TOP");# Set the top module to the most top
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.8 Exclude Test Logic

Some logic in netlist should be ignored in Logic Equivalence Check and ECO, for example, DFT logic or MBIST logic. Several APIs can be used for the excluding purpose, set_ignore_output, set_pin_constant.

For example, the SOC_TOP design should have scan insertion test logic excluded in ECO. The scan out bus pin has naming of scan_out[199:0] and API set_ignore_output can be used to exclude LEC check on scan_out in ECO. And scan_enable and scan_mode are two scan set up signals which can be forced to zeros by API set_pin_constant.

# GofCall ECO script, run_example_exclude_test_logic.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.9 No Exact Pin Match

Physical Synthesis is more and more popular in logic synthesis. Physical Synthesis may add hierarchical pins that are not in RTL code and it may bring mapping issue when Implementation Netlist is comparing with Reference Netlist. API set_noexact_pin_match can be used to resolve the mapping issue between Implementation Netlist and Reference Netlist.

For example, some physical synthesis tool adds 'IN1', 'IN2' ... to hierarchical modules. The new added pins are not necessarily matching to each other in Implementation Netlist and Reference Netlist. They need to be excluded in pin matching. API set_noexact_pin_match is used before loading design.

# GofCall ECO script, run_example_noexact_pin_match.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
set_noexact_pin_match('\bIN\d+\b'); # The argument is in REGEX format
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.10 Flip-flop Phase Inverted

Place and Route tool may invert some flip-flops' phase by moving inverter from input pin to output pin. API set_mapping_method('-phase') is used to handle these flip-flops.

# GofCall ECO script, run_example_ff_phase_inverted.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
set_mapping_method('-phase');
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.11 Cutpoint Method Enable

The Cutpoint Method is to fine tune the ECO result. When an ECO involves one combinational wire change, the Cutpoint Method can produce very small patch. The side effect of the Cutpoint Method is, it runs slow on large ECOs.

# GofCall ECO script, run_example_cutpoint_en.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
set_cutpoint_en(1);
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.12 Dedicated Logic Equivalence Check Engine

The built-in Logic Equivalence Check Engine is dedicated to search equivalent nets in Implementation Netlist to optimize the patch circuit. The searching process is global.

Figure 5: Dedicated LEC Engine

For each net in the Reference Logic Cone, any net in the Implementation Logic Cone with the same fanin end-points is compared for Logic Equivalence.

Users can check equivalence on any two nets in the reference and implementation netlists. The API 'comare_nets' can be used to compare any two nets in Reference Netlist and Implementation Netlist.

Compare_nets API:

Check equivalence of two nets in the reference and implementation netlist

Usage: my $result = compare_net($net0, $net1);
$net0: The net in Reference Netlist.
$net1: The net in Implementation Netlist.
$result: If 1, they are equal, if 0, they are not equal.
Examples:
# Compare reg1/D in the reference and reg1/D in Implementation Netlist
compare_nets("reg1/D", "reg1/D");

2.1.13 Stitch new flops into scan chain

Scan chain can be updated to insert the new flops. 'stitch_scan_chain' command can be used to automatically stitch up the new flops.

For example, eight new flops 'state_new_reg_0' to 'state_new_reg_7' are added in fix_design command. To insert them to the scan chain before 'pulse_reg'

stitch_scan_chain('-to', 'pulse_reg');

The scan chain can be reconnect up by manual change_pin commands as well.

2.1.14 Add a new module

The module mentioned in the section above can have hierarchy kept instead of flatten, and being written into ECO netlist as whole. This flow needs the module and its sub-modules written out in a separate verilog file, then uses read_library to load the file with '-vmacro' option. GOF treats the module as a leaf cell.

An example for adding a new module:

# GofCall ECO script, run_new_module_example.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_hier_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_library("-vmicro", "syn_macro.v");
read_design("-ref", "reference.gv");# Read in the Reference Netlist
# Read in the implementation netlist which is under ECO
read_design("-imp", "implementation.gv");
set_top('top');# Set the top module
fix_design;
report_eco();# ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter

The content in file syn_macro.v is written into the ECO file eco_verilo.v as a whole. The corresponding instance is created as well with ports connected correctly according to Reference Netlist.

2.1.15 Note in RTL modification and re-synthesis

When modifying RTL and do re-synthesis, care should be taken to maintain the database as much alike Implementation Netlist as possible.

2.1.15.1 Keep sequential signal name

A common problem in modifying RTL is having sequential signal name changed, which appears in Reference Netlist as a different flop instance. For example

always @(posedge clk) abc <= abc_next;

It creates a flop instance 'abc_reg' in synthesis. If the ECO in RTL change this to

always @(posedge clk) abc_new <= abc_next;

After synthesis, a new flop instance 'abc_new_reg' is created. GOF may fail to find that 'abc_new_reg' being able to merge with 'abc_reg', due to other non-equivalent points present, which brings a redundant fix in the new register creation.

So it is highly recommended to keep the sequential signal names.

2.1.15.2 Use the same synthesis constraints

When do re-synthesis, the same constraints should be used as what has been used in Implementation Netlist synthesis. If any hierarchy is not present in Implementation Netlist, flattening command should be used in synthesis to flatten the module to the maintain the same hierarchies.

2.1.16 Check design after ECO

It is highly recommended to run 'check_design' after ECO, to speed up, users can specify '-eco' option,

check_design('-eco')

It can detect if there is any floating or multiply drivers after ECO.

2.2 Automatic Metal Only ECO Flow

2.2.1 Overview

 

In Metal Only ECO, the design has completed place and route. Any new gates added should map to spare gates that located in the design.

Figure 6: Metal Only ECO

The flow can use internal synthesis engine or external synthesis tool to map patch logic to spare types. It requires one of the spare type combinations as the following

  • Two ports 'and/or' gates and 'inv' gates, 'mux' is optional.
  • Two ports 'nand/nor' gates and 'inv' gates, 'mux' is optional.

A Design Exchange Format file is needed to map new instances to the closest spare gate instances. If DEF file is not loaded, GOF processes the ECO with gates type from the spare list without mapping to the exact spare instances. P&R tool like SOC Encounter maps the new instances in the new netlist to the closest spare gates.

In 'fix_design' command, GOF analyzes the top level module and its sub-modules to isolate the non-equivalent points and optimize the logic cone to find the minimum gate count patch circuit.

The flow can use external Synthesis Tool as well. The executable synthesis command should be in the search path. The supported Synthesis Tool is RTL Compiler from Cadence and Design Compiler from Synopsys.

GOF writes out the patch in Verilog file and a TCL script for external Synthesis Tool if it's enabled. The TCL script is to constrain the Synthesis Tool to use spare gates only when remapping the gates in the patch file. The Synthesis Tool is run with the Verilog file and TCL script as inputs, and it writes out remapped Verilog patch file which has only spare gate types.

When the spare-only patch file is created, user can pause the flow by '-pause' in 'map_spare_cells' command. User can either modify the patch file manually or tunes up the constraint file to rerun the synthesis for several iterations until the patch netlist meets the requirement. Then press 'n' key to resume the flow.

GOF reads back the spare-only patch file and fits the circuit into Implementation Netlist to fix the logic cones.

When ECO is done, a report can be created and ECO netlist/ECO script can be written out for the back end tool and LEC tool.

2.2.2 Files and data requirements

  • Standard library (Synopsys Liberty) files with extension '.lib'.
  • Other Verilog libraries if '.lib' files can’t cover.
  • Implementation Netlist.
  • Reference Netlist.
  • DEF (Design Exchange Format) file. It’s optional. If it is not loaded, GOF won’t map the spare gate type cells to the exact spare instances.
  • Spare gates pattern. It is in 'hierarchical_instance/leaf_instance' format. It has wild card '*' to match the spare gates in Implementation Netlist.
  • Spare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And new spare gates list file must be created every time an ECO is done.

2.2.3 Steps to do automatic Metal Only ECO

A typical process for an automatic Metal Only ECO:

  • Change RTL modules
  • Synthesize the new RTL to get Reference Netlist
  • Draft a GofCall script:
  • Load Standard Cell libraries and Verilog libraries.
  • Load Reference Netlist and Implementation Netlist.
  • Add 'fix_design' command.
  • Load DEF file, optional.
  • Load LEF file, optional. It's useful in LayoutViewer feature.
  • Create Spare Gates List by Spare Gates pattern or by reading in spare list file.
  • Run 'map_spare_cells' to remap the patch from 'fix_design' command to all spare -type gates patch netlist and select the closest spare instances for each gate in the patch netlist.
  • Report ECO status and write out ECO results.
  • Run the above GofCall script

 

2.2.4 Example GofCall script for Metal Only ECO

The GofCall script has the exact same syntax of Perl script. But it can execute exported commands that access the netlist database and modify the netlist.

The following shows an example of an automatic Metal Only ECO:

# GofCall ECO script, run_metal_only_example.pl
use strict;
undo_eco;# Discard previous ECO operations
# Setup ECO name
setup_eco("eco_metalonly_example " );
 
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module that ECO is working on
fix_design;
# The following is metal ECO related
read_def("topmod.def");# Read Design Exchange Format file, optional
# Specify spare cell pattern, when 'map_spare_cells' is done, a new spare list file is written out
# with updated spare list.
get_spare_cells("*/*_SPARE*");
# Comment the above line and use the following line to use spare list file
# if the spare list file has been generated already and gone through other ECOs
# get_spare_cells("-file", "spare_list_file.txt");
map_spare_cells();
# Use one of the following lines if external Synthesis Tool is used
#map_spare_cells ( "-syn", "rc" );
#map_spare_cells ( "-syn", "dc_shell" );
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
 
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.2.5 Run and debug

The GofCall Script can be run by '-run' option.

gof -run run_metal_only_example.pl

User can insert 'die' command to let GOF stop in some point and do interactive debugs when ‘GOF >’ shell appears. GUI mode can be enabled by run 'start_gui' command.

Check Run and debug GofCall script section for more detail

2.2.6 Gated clocks in AutomaticMetal Only ECO

If the automatic metal only ECO has new gated clock cells added while the spare gates list doesn't have gated clock cell, "convert_gated_clocks" API should be run to convert gated clock cells to 'MUX' type logic. GOF maps the 'MUX' type logic to the spare type gates in 'map_spare_cells' API.

get_spare_cells("*/*_SPARE*");
Convert_gated_clocks();
map_spare_cells();

2.3 Script Mode Full Layers Manual ECO Flow

2.3.1 Overview

In many cases, the ECO operations are well known by users. They can be inserting buffers to a 128bits bus, or adding isolation AND gates to all outputs of a module. In these cases, manual ECO by scripts is more efficient and resource saving.

GOF exports many APIs for ECO operations in GofCall script.

2.3.2 Steps to do Manual ECO In Scripts

A typical situation for a Manual ECO:

  • Run LEC on modified RTL to Implementation Netlist.
  • Collect the failing points in the above run.
  • Draft a GofCall script:
  • Define ECO name in ‘setup_eco’.
  • Load Standard Cell libraries and Verilog libraries.
  • Load Implementation Netlist.
  • Locate ECO point.
  • Use ECO APIs to fix the logic.
  • Run the script.
  • Report ECO status and write out ECO results.

2.3.3 Locate ECO point

Locating ECO point is the hardest part in manual ECO. Wire names in RTL codes are normally optimized away by synthesis process. GOF has a feature to retrieve the nets. Check here for the GUI way or use API ' get_match_nets' in GofCall script.

2.3.4 Files and data requirements

  • Standard library (Synopsys Liberty) files with extension ‘.lib’.
  • Other Verilog libraries.
  • Implementation Netlist.
  • ECO locations.

 

2.3.5 ECO APIs list

These APIs change Implementation Netlist

change_pin: Modify pin connection in ECO.
change_gate: Modify an instance type in ECO.
change_net: Change an existing net's driver.
change_port: Change an output port's driver.
new_net: Create a new net.
new_gate: Create a new gate instance.
new_port: Create a new port.
del_net: Delete a net.
del_gate: Delete a gate.
del_port: Delete a port.

 

For the full list of the APIs, user can type 'help' in 'GOF >' shell.

For the individual API, type 'help api_name' . For example:

GOF > help new_port
Help for new_port
new_port: ECO command. Create a new port for the current top level module
ECO command. Create a new port for the current top level module
Usage: new_port($name, @options);
$name: Port name
@options:
-input: New an input port
-output: New an output port
-inout: New an inout port
Note: The port name has to be pure words or with bus bit, like, abc[0], abc[1]
Examples:
new_port('prop_control_en', '-input'); # create an input port naming 'prop_control_en'
new_port('prop_state[2]', '-output'); # create an output port with bus bit 'prop_state[2]'
new_port('prop_state[3]', '-output'); # create an output port with bus bit 'prop_state[3]'

2.3.6 Example GofCall script for Manual ECO

# GofCall ECO script, run_example.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in implementation Netlist Which is under ECO
set_top("topmod");# Set the scope to the module that ECO is working on
 
# The following API adds a mux in flop 'state_reg_0_' D input pin,
# and connect up the original connection to pin 'A',
# pin 'B' connect to net 'next_state[7]', and pin 'S' to net 'sel_mode'
# the net can be replaced by format of 'instance/pin' , E.G. '.S(state_reg_2_/Q)'
change_pin("state_reg_0_/D", "MX2X4", "", ".A(-),.B(next_state[7]),.S0(sel_mode)");
 
report_eco();
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
 
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.3.7 Run and debug

Check Run and debug GofCall script section for more detail

 

2.3.8 Handle repetitive work

A Perl 'for' or 'foreach' loop can handle repetitive work efficiently. For example, to add a 'AND' isolation gate for every output port of a module.

# GofCall ECO script, add_ands.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in implementation Netlist which is under ECO
set_top("topmod");# Set the top module that ECO is working on
my @ports = get_ports("-output");# Get all output ports of module 'topmod'
# For each output port of 'topmod', insert an 'AND' gate to enable it only when 'enable_out' is high
foreach my $port (@ports){
  change_port($port, "AND2X2", "", "-,enable_out");
}
 
report_eco();
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
 
gexit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

 

2.3.9 Special character

The special character '-' is used to represent existing connection. For example

change_pin("U0/A", "BUFFX1", "eco_buf","-");

A buffer is inserted into A pin of instance U0. The old existing net drives the new buffer now.

 

The special character '.' is used in ECO new instance name if the new instance needs to be in the same hierarchy as the ECO spot.

change_pin("u_qcif/u_num2/u_spare1/B", "AOI21X2",".", "net1,net2,net3");

If the instance is empty, GOF creates 'AOI21X2' in the current top level. With ".", GOF creates 'AOI21X2' new instance in hierarchy "u_qcif/u_num2/u_spare1".

 

2.4 Script Mode Metal Only Manual ECO Flow

2.4.1 Overview

In Manual Metal Only ECO, any new added gates are automatically mapped to spare gate instances by 'map_spare_cells' command. A Design Exchange Format file has to be loaded for the tool to find optimal spare instances. If the file is not present, the mapping is skipped.

2.4.2 Files and data requirements

  • Standard library (Synopsys Liberty) files with extension '.'lib'.
  • Other Verilog libraries.
  • Implementation Netlist.
  • DEF (Design Exchange Format) file. If it is not loaded, GOF won’t map the spare gate type cells to the exact spare instances.
  • Spare gates pattern. It is in ‘hierarchical_instance/leaf_instance’ format. It has wild card '*' to match the spare gates in Implementation Netlist.
  • Spare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And a new spare gates list file should be created every time ECO is done.
  • ECO locations.

 

2.4.3 Example GofCall script for Manual Metal Only ECO

# Manual Metal Only ECO, manual_metal_eco.pl
use strict;
undo_eco;
setup_eco("metal_eco0123");
set_log_file("metal_eco0123.log");
read_library("/prj/lib/tsmc40.lib");
read_design("-imp", "/prj/netlist/imp_net.v");
set_top("mtop");
 
new_port("nout7", "-output");# Create a new port 'nout7'
# Place the port to 60000, 1000000. It's approximate position, the main purpose is for
# spare instances selection
place_port("nout7", 60000, 100000);
new_port("nout8", "-output");# Create another port
place_port("nout8", 120000, 81000);
# 'nout8' is driven by an invert first, and the invert's input is driven by pin 'cmpmod/rego/QN'
change_port("nout8", "INV_X1M", "", "cmpmod/rego/QN");
# Drive the 'nout7' by 'INV_X1M' and leave the input unconnected, but the mapped
# spare instance name is returned.
my $inst = change_port("nout7", "INV_X1M", "", "");
# Drive the new instance's input by a flop, and specify the flop's connection in the 4thargument
change_pin("$inst/A", "SDFFRPQ_X4M", "", \
".CK(cmpmod/rego/CK),.D(cmpmod/rego/QN),.R(1'b0),.SE(1'b0),.SI(1'b0)");
 
read_def("/prj/def/imp_net.def");
get_spare_cells("Spare_*/*_SPARE_GATE*");
# Before mapping to spare gates, set a large number in buffer distance, so that GOF does not
# add buffers for long connections.
set_buffer_distance(9999999);
# The following 'map_spare_cells' command maps the three new ECO instances to the optimal
# spare instances.
map_spare_cells;
 
report_eco;
write_verilog("imp_eco0123.v");

2.4.4 Run and debug

The GofCall Script can be run by ‘-run’ option.

gof -run manual_metal_eco.pl

Check Run and debug GofCall script section for more detail

2.5 GUI Mode Full Layers ECO Flow

2.5.1 Overview

The following paragraph demonstrates how to insert buffers and inverters into a circuit in GUI mode.

 

2.5.2 Start up GOF in GUI Mode

 

Start up Gates On the Fly by the command line

gof -lib t65nm.lib -lib io.lib netlist_port.v

For detail usage, visit this link

https://nandigits.com/usage.htm

In GofViewer netlist window, press ctrl-g or menu commands->’Launch GofTrace with gate’. Fill in the instance name that needs ECO.

Figure 7: Load gate to schematic

2.5.3 Create Partial Schematic

In GofTrace schematic window, use mouse middle button to expand the schematic. In this case, pin D of the flop should be inserted an invert.

Figure 8: Partial Schematic for GUI ECO

 

2.5.4 Do ECO on schematic

 

Check ECO button to enable ECO mode

Figure 9: Schematic in ECO Mode

Press mouse-left-button on the wire to select it. Click ECO button ‘Insert gates into connections’, select the right invert in the gate type selection window.

Figure 10: Select Gate in GUI ECO

In ‘Pin Connections’ setup window, use default ‘Complete Loop’ option, so that the gate can be inserted in the net.

Figure 11: New Cell Pin Connection Selections

 

Click OK and the invert is inserted.

Figure 12: Manual ECO with New Gate Inserted

2.5.5 Save ECO

Press ECO button ‘Save ECO result to file’. And select the format to be saved. The supported formats include verilog netlist, SOC Encounter ECO script, GofCall Script, TCL script and DCShell script.

Figure 13: Save ECO in GUI Mode

2.6 GUI Mode Metal Only ECO Flow

2.6.1 Overview

Metal ECO can only use existing spare gates on the silicon. Gates On the Fly controls how to use these spare gates.

2.6.2 Methods for Metal Only ECO

Four methods are supported in Metal Only ECO:

  1. User can add any type of gates and let the tool map to the spare type gates, Place and Route tool should map the spare type gates to the exact spare gate instances.
  2. User can add any type of gates and let the tool map to the exact spare gate instances.
  3. User can add only spare type gates and let the tool map to the exact spare gate instances.
  4. User can pick the exact spare gate instances, and connect and disconnect up the instances in ECO.

Note: 'Spare type gate' refers to the gate type, 'INVX2', 'NAND2X2'. 'Exact spare gate instance' refers to the spare instances in the design, E.G. 'spare1/spare_invx2'

2.6.3 Setup and use cases

The detail setup for four method can be found in GofECO Metal Only ECO. Use cases can be found in online document.

3 Script Mode Detail Features

3.1 GofCall Script

GofCall is the Perl Script Interface which can access internal exported APIs.

3.1.1 Get Help

  • Type 'help' in interactive shell 'GOF >' to list all APIs.
  • Type 'help set_*' to list all APIs matching 'set_', like 'set_top', 'set_invert'
  • Type 'help individual-API' to list detail of the API.
  • Visit https://nandigits.com/gof_manual.htm for online manual.

 

3.1.2 Feature list

  • Compatible with Perl.
  • Automatic ECO with fix_design/fix_modules APIs.
  • Rich ECO APIs to do manual ECO.
  • ECO operations are reversible.
  • ECO result can be loaded in schematic on the fly.
  • Integrated commands to browser netlist and check design status

3.1.3 API list

buffer: ECO command. Buffer high fanout ECO nets
change_gate: ECO command. Modify an instance in ECO
change_net: ECO command. Change a existing net's driver
change_pin: ECO command. Modify pin connection in ECO
change_port: ECO command. Change an output port's driver
check_design: Check if the netlist status
compare: Logic equivalence check on output port and register input pins
compare_nets: Check equivalence of two nets in the reference and implementation netlist
convert_gated_clocks: ECO command. Convert gated clocks to MUX logic
current_design: Set the current top level module
current_instance: Set the current instance
del_gate: ECO command. Delete gate
del_net: ECO command. Delete net
del_port: ECO command. Delete port
exist_inst: Check if an instance exists
exist_wire: Check if a wire exists
fix_design: ECO command. Fix the whole design in global mode
fix_hold: ECO command. Fix hold time violations.
fix_logic: ECO command. Fix listed points
fix_modules: ECO command. Fix modules listed in the arguments
fix_setup: ECO command. Fix Setup time violations.
flatten_modules: Flatten hierarchical modules in reference netlist
get_cell_info: Get information of a module or instance
get_cells: Get all cells in the current module or sub-modules
get_conns: Get connections of net or pin in the top level module
get_coord: Get an instance's coordination
get_definition: Get instantiation of instance
get_driver: Get the driver of a net or pin
get_drivers: Get the drivers of a net or pin
get_instance: Get instance in the top level module
get_instances: Get all hierarchical instances in the top level module
get_leaf_pin_dir: Get leaf cell pin's direction input/output/inout
get_leafs_count: Get all leaf cells name and count in the top level module
get_lib_cells: Get leaf gates in libraries
get_loads: Get loads of net or pin in the top level module
get_logic_cone: Get logic cone of nets or pins
get_match_nets: Get logic equivalent nets in implementation netlist
get_modules: Get all hierarchical modules under current module
get_net_of: Get net name connecting to a pin
get_nets: Get nets that matching pattern
get_path: Get current hierarchical path
get_pins: Get pins of instance or module
get_ports: Get all ports in the current top level module
get_ref: Get the reference of the instance
get_resolved: Resolve the relative path to module and leaf item
get_roots: Get root designs name
get_spare_cells: ECO command. Get spare cells
gexit: Exit the GofCall interactive mode
gprint: Print out the message and save to log file
is_leaf: Check if a module or instance is leaf cell
is_seq: Check if a leaf module is a specific sequential cell
lv_search: Search instances in LayoutViewer window
map_spare_cells: ECO command. Map all new created cells to spare cells
new_gate: ECO command. Create new gate
new_net: ECO command. Create a new net
new_port: ECO command. Create a new port for the current top level module
place_gate: ECO command. Place gate position
place_port: ECO command. Place port position
pop_top: Pop out the saved top level module from the stack and discard the current setting
push_top: Set the current top level module and push the previous setting to stack
read_def: Read DEF file
read_design: Read verilog netlist
read_file: Read timing violation report file
read_lef: Read LEF file
read_library: Read standard library or verilog library files
rename_net: ECO command. Rename a net name
report_eco: Report ECO
report_spares: Report Spare cells
run: Run GofCall script
sch: Launch schematic to verify ECO
set_auto_fix_floating: ECO setting. Enable automatic fixing floating input ports after fix_modules
set_bfix: Enable or disable BFIX features
set_bound_opti: Enable or disable boundary optimization check. Enabled by default
set_buffer: Set buffer type. The tool automatically picks one if the command is not called
set_buffer_distance: Set distance limit for inserting buffer
set_constraints: Set constraints for map_spare_cells command
set_cutpoint_en: Enable or disable CutPoint Method
set_cutpoint_thresh: Set Cutpoint Threshold
set_cutpoint_ultra: Enable or disable CutPoint Ultra Effort
set_dont_use: Set dont use list
set_eco_effort: ECO setting. Set ECO effort
set_equal_net: ECO setting. Set two nets to be equivalent in Reference and Implementation netlists
set_exit_on_error: Whether the tool should exit when the script runs into an error
set_exit_on_warning: Whether the tool should exit when the script runs into a warning
set_ignore_instance: ECO setting. Set ignored sequential or blackbox instances in ECO
set_ignore_network: ECO setting. Set ignore network in ECO
set_ignore_output: ECO setting. Set ignore output ports
set_inside_mod: Set fix scope inside the current module
set_inst: Set the current instance
set_inv_net: ECO setting. Set two nets to be inverted in Reference and Implementation netlists
set_invert: Set invert type. The tool automatically picks one if the command is not called
set_keep_format: Set keep format of the original verilog when ECO is done
set_keep_tree: Set keeping buffer tree
set_leaf: Set a hierarchical module to be leaf. Useful to stub hierarchical instances
set_log_file: Set log file name
set_max_lines: Set max output lines
set_max_loop: Setup max loop
set_mod2mod: Set reference module mapping to implementation module
set_mu: MU configuration
set_noexact_pin_match: ECO setting. Don't match some special pins
set_pin_constant: Set pin to a constant value
set_power: Set power pins connections for leaf cell
set_preserve: Set preserve property on instances. The tool does not remove them in ECO
set_quiet: Run script in quiet mode
set_recovery_distance: Set distance limit for gates recovery in ECO
set_tiehi_net: Set tiehi net name
set_tielo_net: Set tielo net name
set_top: Set the current top level module
set_tree: Set the current tree
set_user_match: Set match between multi-bit flops to multi-bit flops
set_verbose: Run script in verbose mode
setup_eco: ECO command. Setup ECO
source: Run GofCall script
start_gui: Start GUI windows
stitch_scan_chain: ECO command. Stitch scan chain
suppress_warnings: Suppress warning messages
swap_inst: ECO command. Swap two instances with same input/output pins.
undo_eco: ECO command. Undo eco operations
write_dcsh: ECO command. Write ECO result in Design Compiler dcsh script format
write_perl: ECO command. Write GofCall ECO script compatible with Perl
write_soce: ECO command. Write ECO result in Cadence SOC Encounter script format
write_spare_file: ECO command. Write spare cells list to a file
write_tcl: ECO command. Write ECO result in Design Compiler tcl script format
write_verilog: ECO command. Write ECOed netlist to a verilog file

3.1.4 API grouping

3.1.4.1 Netlist Browse APIs

One key element to do efficient manual ECO is to isolate the ECO spots quickly. The following APIs are for fast Netlist Browsing.

get_cells: Get all cells in the current module or sub-modules
get_conns: Get connections of net or pin in the top level module
get_driver: Get the driver of a net or pin
get_drivers: Get the drivers of a net or pin
get_instance: Get instance in the top level module
get_instances: Get all hierarchical instances in the top level module
get_leaf_pin_dir: Get leaf cell pin's direction input/output/inout
get_lib_cells: Get leaf gates in libraries
get_loads: Get loads of net or pin in the top level module
get_match_nets: Get logic equivalent nets in implementation netlist
get_modules: Get all hierarchical modules under current module
get_net_of: Get the net name connecting to the pin
get_nets: Get nets that matching pattern
get_pins: Get pins of instance or module
get_ports: Get all ports in the current top level module
get_ref: Get the reference of the instance
 

For example, to get all flops' data pins in one module. The script can use these browse APIs

my @flop_data_pins;
set_top("module_name");
my @flops = get_cells("-type", "ff");
foreach my $flop (@flops){
  my @dpins = get_pins("-data", $flop);
  push @flop_data_pins, @dpins;
}

 

After the script is run, @flop_data_pins have all data pins of all flops in the module.

 

3.1.4.2 Automatic ECO APIs

These APIs are for Automatic ECO

fix_design: ECO command. Fix top level module and its sub-modules
fix_modules: ECO command. Fix modules listed
map_spare_cells: ECO command. Map all new created cells to spare cells
fix_logic: ECO command. Fix listed points
 

Combining netlist browsing APIs, users can come up a short script to do complicated changes.

For example, to fix all modules named "tx_machine_*"

my @modules = get_modules("-hier", "tx_machine_*");
fix_modules(@modules);

3.1.4.3 File IO APIs

These APIs are for reading/writing files.

read_def: Read DEF file
read_design: Read verilog netlist
read_file: Read timing violation report file
read_lef: Read LEF file
read_library: Read standard library or verilog library files
write_dcsh: ECO command. Write out ECO result in Design Compiler dcsh script format
write_perl: ECO command. Write out GofCall ECO script compatible with Perl.
write_soce: ECO command. Write out ECO result in Cadence SOC Encounter script format
write_spare_file: ECO command. Write out spare cells list file
write_tcl: ECO command. Write out ECO result in Design Compiler tcl script format
write_verilog: ECO command. Write out ECOed netlist to a file

3.1.4.4 Manual ECO APIs

These are APIs for Manual ECO.

buffer: ECO command. Buffer high fanout ECO nets
change_gate: ECO command. Modify an instance in ECO.
change_net: ECO command. Change a existing net's driver
change_pin: ECO command. Modify pin connection in ECO.
change_port: ECO command. Change an output port's driver
del_gate: ECO command. Delete gate
del_net: ECO command. Delete net
del_port: ECO command. Delete port
new_gate: ECO command. Create new gate
new_net: ECO command. Create a new net
new_port: ECO command. Create a new port for the current top level module

Combining netlist browsing APIs, a short GofCall script can do very efficient ECOs.

For example, to add isolation cells for all output ports of a module.

set_top("module_name");
my @out_ports = get_ports("-output");
foreach my $out (@out_ports){
  change_port($out, "AND2X2", "", "-,net_iso_enable");
}

 

3.1.5 API usage

For detail of APIs visit https://nandigits.com/apis_gof.htm

For individual API, type '#' followed by API_name.

For example, to check usage of 'change_pin'

https://nandigits.com/apis_gof.htm#change_pin

 

3.2 String Handling In Script Mode

3.2.1 Single quote and double quote

 

Any string in GofCall script for module/instance/wire/pin/port should be enclosed by single quote or double quote. When a Perl variable is used, double quote should be used

my $inst = "state_reg_0";
change_pin("$inst/D","1'b0");

3.2.2 Instance and net with backslash

 

Instance with backslash should be either put in single quote and with a space in the end, or removed the backslash and let the tool to figure out the real name.

'\u_abc/u_def/state_reg[0] ' can be written as 'u_abc/u_def/reg_state_0[0]'

Net name with backslash should always keep the backslash. One good way to avoid write net name directly is to use 'instance/pin' format. For example

DFFQ_X4M \u_abc/u_def/state_reg[0] (.D(\u_abc/u_def/net123 ), .Q(\u_abc/u_def/state[0] ));

The net '\u_abc/u_def/net123 ' can be replaced by 'u_abc/u_def/state_reg[0]/D' and

The net '\u_abc/u_def/state[0] ' can be replaced by 'u_abc/u_def/state_reg[0]/Q'

3.3 Run and debug GofCall script

3.3.1 Command line

In command line, the GofCall Script can be run by ‘-run’ option.

gof -run run_example.pl

3.3.2 GOF Shell

If '-run' option is present in the command line, and 'gexit' is not in the script, or GOF meets error when executing the script, GOF goes to interactive mode with GOF shell 'GOF >'.

GofCall, Netlist Processing Script APIs, Interactive Mode
Run 'start_gui' to launch GUI window
Run 'help' to list API calls
GOF >
 

Individual command can be executed in GOF shell. The command can be in nested mode

GOF > set_top(get_ref("u_rxbuf"))

3.3.3 Run in GUI mode

GofCall scripts can be run in GUI window. In GofViewer, click Menu Commands->’Launch GofCall Script Interface’ to launch GofCall GUI window.

Type ‘help’ in the shell entry for help information. Scripts can be run by ‘run’ command in the shell entry

Figure 14: GofCall window

3.3.4 Fast schematic launch

In GOF shell, GUI windows can be launched by 'start_gui' or 'sch' commands.

'start_gui' launches netlist view window first and user can bring up schematic window from netlist view window.

'sch' command only launches schematic window, and it doesn't enable netlist view window. So it has fast turnaround in GUI interactive debug.

For example,

After the following command is done,

change_pin("u_top/u_core/u_regmod/state_reg/D", "XOR2X2", "", "-,new_enable");

Run 'sch' in 'GOF >'

GOF > sch("u_top/u_core/u_regmod/state_reg")

The instance is loaded into a schematic and user can click on the instance's pins to trace fanin/fanout on the schematic to see if the ECO is done as expected.

3.3.5 Break points for debug

'sch' fast schematic launch command can be used as break points for debug. For example, 'sch' commands are inserted in GofCall script, when the tool runs to the point, a schematic is launched.


setup_eco("sanity75");
set_log_file("t_sanity75.log");
read_library("libdr/art.m.simple.lib");
read_design('-imp', "cdir/imp_name.v");
change_pin("state_reg_0_/D", "MX2X4", "", ".A(-),.B(next_state[7]),.S0(sel_mode)");
sch("state_reg_0_", "-set", 1);

 

On the schematic, user can use mouse-middle-button clicking on the pin 'D' to see if the ECO is done as expected.

 

 

Figure 15: Launch schematic at break point

Note: 'ECO' check-button is enabled automatically, since there is ECO having been done.

To compare with the logic before ECO, launch a new schematic by menu Schematic->'New Schematic'. On the new schematic, press 'ctrl-g' or by menu Schematic->'Load Gate' to load in the flop under ECO.

Figure 16: Launch schematic before ECO

Note: 'ECO' check-button is un-checked.

3.4 Typical Manual ECO operations

3.4.1 Insert gate to port

Both input port and output port have the same operation

3.4.1.1 Insert an invert to input port

# Insert to input port 'in_enable'
change_port("in_enable", "INVX1", "inst_name", "-"); # 'inst_name' can be empty
 

3.4.1.2 Insert to output port

# Insert AND2X1 to output port 'out_enable', one pin connects to the original driver,
# the other pin is driven by 'scan_mode'
change_port("out_enable", "AND2X1", "", "scan_mode,-");

3.4.1.3 Insert inverts to multiple ports

# Find all ports matching string "abcde" and insert invert to each port
my @ports = get_ports("*abcde*");
foreach my port (@ports){
 change_port($port, "INVX1", "", "-");
}

 

3.4.2 Insert gate to register instance pin

3.4.2.1 Insert invert to flop data pin

# Insert an invert to 'D' pin of flop 'abc_reg'
change_pin("abc_reg/D", "INVX1", "", "-");
 

3.4.2.2 Insert invert to flop output pin

# Insert an invert to 'Q' pin of flop 'abc_reg'
change_pin("abc_reg'Q", "INVX1", "", "-");

3.4.2.3 Insert MUX to data pin of multiple flops

# Find all flops matching string "cnt_reg" and insert MUX to 'D' pin of each flop,
# so that each flop is preset to 'preset_val' when 'preset_enable' is high
my @flops = get_cells("*cnt_reg*");
foreach my $flop (@flops){
 change_pin("$flop/D", "MUX2X2", "", ".A(-),.B(preset_val),.S(preset_enable)");
}

3.4.3 Change flops to other type

3.4.3.1 Change non-reset flop type to resettable flop

# Find all flops matching string "cnt_reg" and change each flop to resettable flop
my @flops = get_cells("*cnt_reg*");
foreach my $flop (@flops){
  change_gate($flop, "DFFRQX2", ".RD(reset_n)");
}

3.4.4 Insert gate to hierarchical instance pin

3.4.4.1 Insert invertsto hierarchical instance pins

# Find all instances matching "tx_mac" in module "abc_mod" and insert invert to 'loop_en' pin
set_top("abc_mod");
my @insts = get_instances("*tx_mac*");
foreach my $inst (@insts){
  change_pin("$inst/loop_en", "INVX1", "", "-");
}

3.4.4.2 Insert AND to hierarchical instance pins

# Find all instances matching "tx_mac" in module "abc_mod" and
# AND all output pins with "power_on" signal.
set_top("abc_mod");
my @insts = get_instances("*tx_mac*");
foreach my $inst (@insts){
  my @pins = get_pins("-output", $inst);
  foreach my $pin (@pins){
    my $net = get_net_of($pin); # Only add AND to those out pins driving nets
    if($net){
      change_pin($pin, "AND2X2", "", ".A(-),.B(power_on)");
    }
  }
}

 

4 GUI Mode Detail Features

4.1 GofViewer

When GOF is run without '-run' and '-shell' option, it goes into GUI mode.

gof -lib t65nm.lib -lib io.liblong_port.v

GofViewer is the first window after GOF starts up GUI interface.

Figure 17: GofViewer Window

 

4.1.1 Log Window

If there errors or warnings in loading the database, Log Window pops up

Figure 18: Log Window

 

4.1.2 File Menu

4.1.2.1 Load Design

Users can input netlist files and design files through the Load Design command.

4.1.2.2 Reload Design

If any netlist file or design file has been updated during GOF session, this command can be used to reload the design.

4.1.2.3 Open Other Netlist

This command loads another netlist file to create a new hierarchical tree. The hierarchy tree is listed in the hierarchy list window. The command is useful when users want to draw circuits from different netlist file on the same schematic which is good for logic comparison in netlist debug scenario such as LEC failures analysis.

4.1.2.4 Open Log Window

The command opens log file in a text window.

4.1.2.5 Exit

Exit command.

4.1.3 Find Menu

This command searches for the matching string in the netlist text window.

4.1.3.2 Goto Line Number

GOF loads only one module in the netlist text window when the netlist file is hierarchical with multiple modules. The command loads the corresponding module into the text window and highlight the line with the specific number in the netlist file.

4.1.3.3 Report Area

This command reports the design area. The command requires standard library files to be loaded which include leaf cell area information.

4.1.3.4 Report Leakage

This command reports the leakage power in the design. Same as the Report Area command it requires standard libraries.

4.1.3.5 Report Leaf Cells

This command reports the leaf cell type and numbers in the design.

4.1.3.6 Report Submodules

This command reports the hierarchical sub-modules in the design.

4.1.3.7 Statistic of Current Design

This command reports the statistic of the current design. It pops up an option window for interactivity from users.

4.1.3.8 List Library

The command lists the libraries and leaf cells in each library.

4.1.3.9 List Context for Leaf Cell

This command pops up an entry window for users to input leaf cell name string, wild card can be accepted. All leaf cells matching the string is listed. If there is only one cell matched, the detail property is listed.

4.1.4 Commands Menu

4.1.4.1 Launch GofTrace Schematic

This command launches GofTrace Schematic, if any instance or net string is highlighted in the netlist window, the instance or the driver of the net is drawn on the schematic. Otherwise, the schematic is empty.

4.1.4.2 Launch GofTrace with Gate

This command pops up an entry window for users to input a string to load a specific instance. For example, ‘u_abc/U123’. Click ‘OK’ button on the pop window, GofTrace Schematic is launched.

4.1.4.3 Launch Layout Viewer

This command launches Layout Viewer window, if any instance or net string is highlighted in the netlist window, the instance or the driver of the net is highlighted on the Layout Viewer window. The command requires that physical files to be loaded. Both def and lef files should be loaded before launching Layout Viewer, otherwise a warning window pops up for the missing physical files.

4.1.4.4 Launch GofCall Script Interface

This command launches GofCall window to run scripts or other interactive command.

4.1.4.5 Switch to GOF Shell Mode

This command exits GUI mode and switches to shell mode. It has ‘GOF >’ shell interface in shell mode.

4.1.4.6 Spare Cells

This command group processes Spare cells in metal ECO. Warning! GUI metal ECO is used for visually checking the possibility of metal ECO. The script mode metal ECO is recommended.

  • Create Spare Cells File

This command extracts spare cells from netlist file. A pop window appears for spare gates pattern. The default is ‘spare_*/*’.

Figure 19: Spare Cell Pattern

Click 'OK' to extract spare instances from the netlist, and a pop text window appears to list all spare gate instances. Save the list to a spare list file for later usage.

Figure 20: Spare cell list

  • Load Spare Cells File

This command loads in the spare cells file created by the above command.

4.1.4.7 Launch Files Compare Window

This command launches netlist files compare window. The netlist compare function can do more than simple Linux ‘diff’ command.

4.1.4.8 Process Timing Violations

This command processes Prime Time report file. Read this PDF file for the use case.

nandigits.com/use_cases/gof_timing_analysis.pdf

4.1.4.9 SDF

This command group processes SDF file for delay information interactivity.

  • Create SDF Index File

GOF reads in SDF Index File instead of SDF file itself, since SDF can have huge size. Once the index file is created it can be reused next time and loaded in much faster.

  • Load SDF Index File

This command loads in already created SDF Index File.

4.1.5 Options Menu

4.1.5.1 Hierarchy Window Font

Check GofViewer for the hierarchy list window position

  • Increase Font Size

Increase font size in the hierarchy list window.

  • Decrease Font Size

Decrease font size in the hierarchy list window.

4.1.5.2 Netlist Window Font

Netlist window locates in the right side of GofViewer window. Check GofViewer for the netlist text window position

  • Increase Font Size

Increase the font size in netlist window.

  • Decrease Font Size

Decrease font size in netlist window.

4.1.5.3 Dump Waveform Restore File

An option window pops up for users to choose which dump restore file to be saved. It’s useful for netlist simulation debug. When one format box is checked in pop menu, ‘Write Waveform Restore File’ item is presented on the top when one net is selected in the netlist window.

4.1.5.4 Setup

Integration of various setup information.

4.1.6 Help Menu

4.1.6.1 General

General help information.

4.1.6.2 About

About Gates On the Fly.

4.1.6.3 nandigits.com/gof_manual.php

Visit the website for this manual.

4.1.6.4 Read Ethernet Mac Address

Read out MAC address. When users decide to purchase licenses or ask for evaluation licenses, MAC address is required to generate GOF licenses.

4.1.7 Keyboard Shortcuts

4.1.7.1 Access Menu

Press key ‘Alt’ and underlined letter in menu.

4.1.7.2 Functions access

  • Ctrl-a: Select all text lines
  • Ctrl-c: Copy the marked (highlighted) string
  • Ctrl-v: Paste the content in clipboard
  • Ctrl-d: Trace driver of the marked net
  • Ctrl-f : Search function
  • Ctrl-g: Load instance to schematic
  • Ctrl-s: Emacs style search forward
  • Ctrl-r: Emacs style search backward
  • Ctrl-w: Write to waveform dump restore file
  • Ctrl-x: Exit the current window

4.1.8 Selection Status

Click mouse-left-button on netlist text window, the object which can be net, instance or module under the cursor is highlighted. Netlist window pop menu has different content according to the selection status. Pressing keys Ctrl-a can have all content in the netlist window selected. Press mouse-left-button and don’t release, move mouse down to select multiple lines.

4.1.9 Netlist Window Pop Menu

Click mouse-right-button and release, a pop menu appears under the cursor. The menu content varies with the selection status in the netlist window.

4.1.9.1 Search

Search for a string in the netlist window. Keyboard shortcut is Ctrl-f.

4.1.9.2 Copy Selected to

Copy the selected object (net or instance) to new schematic window or existing schematic window.

  • Schematic New

Copy the selected object to a new schematic.

  • Schematic #number

Copy the selected object to an existing schematic window.

4.1.9.3 Driver of the selected net

Trace to the driver of the selected net. The netlist window shows the instance that drives the net and mark the driven net.

4.1.9.4 List Connectivity of the selected net

Pop up a window to list the connectivity of the selected net.

4.1.9.5 List Fanin EndPoints

Pop up a window to list the fanin endpoints including flops and input ports that drive the selected net.

4.1.9.6 List Fanout EndPoints

Pop up a window to list the fanout endpoints including flops and output ports that are driven by the selected net.

4.1.9.7 Parent Module

Go to the definition location of the parent module calling the current module. It’s only active in sub-modules, not in root top level module.

4.1.9.8 List Context

List the context of the selected object which can be net, instance or module.

4.1.10 Hierarchy Window Pop Menu

Click mouse-right-button and release, a pop menu appears under the cursor. The menu content varies with the selection status in the hierarchy window.

4.1.10.1 Show Definition

Open the module content and display it in the netlist window.

4.1.10.2 Show Calling

Open the parent module and highlight the instantiation location.

4.1.10.3 Report Area of the selected design

See Report Area

4.1.10.4 Report Leakage of the selected design

See Report Leakage

4.1.10.5 Report Leaf Cells of the selected design

See Report Leaf Cells

4.1.10.6 Report Submodules of the selected design

See Report Submodules

4.1.10.7 Statistic of the selected design

See Statistic of Current Design

4.1.10.8 Edit Module of the selected design

Edit the module by using edit tool defined in menu Options->Setup->Misc->’Edit tool’. It asks for a directory for storing temporary files.

4.1.10.9 Save Module of the selected design

After editing, the edited modules can be saved into a file.

4.1.10.10 Goto Line Number

4.2 GofTrace

GofTrace is an incremental schematic engine. Users control how to expand the schematic by clicking the input/output pins of gates with mouse-middle-button. Users can adjust the positions of the gates on the schematic any time by mouse-left-button.

Figure 21: GofTrace Window

4.2.1 Mouse buttons usage

4.2.1.1 Mouse Left Button

Mouse left button is used to select object. Click on any object, it is highlighted to indicated being selected. Press 'ctrl' key and click on objects to select multiple objects. Press mouse left button and move the mouse to select multiple objects at one time.

4.2.1.2 Mouse Middle Button

Mouse middle button is used to trace the schematic. Click on input/output pins to expand the schematic. It used to do drag-drop function as well. In ECO mode, it's used to connect floating input pin to existing nets.

4.2.1.3 Mouse Right Button

Mouse right button is to popup menu.

4.2.2 File Menu

4.2.2.1 Save

Save the schematic to a file for future usage. The saved file has extension ‘.st’ which can only be used by GOF in ‘Open’ schematic command shown below.

4.2.2.2 Open

Open schematic stored by Save command above.

4.2.2.3 Print

Print schematic to a printer or file. Printer Page Setup window pops up for the print scope setup. In Windows platform, users can select one of the printers configured in the system. In Linux platform, make sure ‘lpr’ command works.

4.2.2.4 Exit

Exit GofTrace window.

4.2.3 Schematic Menu

4.2.3.1 New Schematic

This command launches a new GofTrace schematic window.

4.2.3.2 List Gate

This command pops up a window for user to enter a string into the entry to find the matching instances. It accepts wildcards in both hierarchy name and instance name. For example, there are four hierarchical instances u_lane0, u_lane1, u_lane_2, u_lane3, each instance has spare modules with instance naming ‘u_spare*’, and in each spare module AND gate has instance naming ‘*AND*’. In order to find all spare AND gates, one can enter a string ‘u_lane*/u_spare*/*AND*’.

4.2.3.3 Load Gate

This command pops up a window for user to enter a string into the entry to load the matching instances onto the schematic. Same as ‘List Gate’ command above, it accepts wildcards. However, the total number of gates drown on the schematic should not exceed the threshold defined in Menu Options->Setup->Misc->’Gates number limit’.

4.2.3.4 Load Gate Driving Net

This command pops up a window for user to enter a string into the entry as the net name. The tool finds the driver of the net and draw the driver on the schematic.

4.2.3.5 List Selected Instances

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected instances’ full hierarchical names in a pop window.

4.2.3.6 List Selected Wires

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected wires’ full hierarchical names in a pop window.

4.2.3.7 List Selected Modules

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected gates’ module name in a pop window.

4.2.3.8 List Selected Instances Definitions

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected instances’ full definitions in a pop window.

4.2.3.9 List Selected Gates Types

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list logic type numbers of all the selected gates in pop window. For example, ‘AND’ gate has type ‘and’, inverter has type ‘not’. The pop window can have information such as “Type ‘not’ has 11”.

4.2.3.10 Zoom In

This command can zoom in the schematic view. The maximum zoom in ratio is 100%. Keyboard shortcut for this command is key ‘+’.

4.2.3.11 Zoom Out

This command can zoom out the schematic view. The minimum zoom out ratio is 13%. Key board shortcut for this command is key ‘-‘.

4.2.3.12 Zoom to

This command can directly select zoom ratio, the valid values are 100%, 67%, 44%, 30%, 20% and 13%.

4.2.3.13 Find Gates on Schematic

This command pops up a window for users to enter a string to find the matching instances on the schematic. It matches portion of the full name. For example, ‘U’ matches ‘U0’, ‘U1’ and ‘U222’.

4.2.3.14 Find Nets on Schematic

This command pops up a window for users to enter a string to find the matching wires on the schematic. It matches portion of the full name. For example, ‘Net0’ matches ‘Net0’, ‘Net011’ and ‘Net023’.

4.2.3.15 Undo Schematic Operations

This command is to undo schematic operations. Keyboard shortcut is Ctrl-z.

4.2.3.16 Place and Route

This command group is to automatically place the gates on the schematic and automatically route the wires.

  • Auto Place and Route

This command is to do both placement and routing automatically.

  • Auto Place

This command is to do automatic placement only.

  • Auto Route

This command is to do automatic routing only.

  • Reset Route

This command is to reset all existing routes, all routed wires become straight.

4.2.3.17 Create PS/PDF File

This command is to create Postscript file or PDF file for the current view of the schematic. In Windows platform, only Postscript is support. On Linux platform both Postscript and PDF are supported.

4.2.4 Commands Menu

4.2.4.1 View Gates in Layout

This command launches layout viewer window. If some gates and wires are selected on the schematic, they are highlighted on the layout viewer. It requires DEF and LEF physical design files to be loaded.

4.2.4.2 Load Layout Files

This command is to load layout physical design files. They include DEF and LEF files. The command can be run several times to load the physical design file one by one. DEF and LEF files can be loaded by command line with -def and -lef options. Or they can be read in by API 'read_def' and 'read_lef' in GofCall script.

4.2.4.3 Launch GofCall Script Interface

This command launches GofCall Script Interface window.

4.2.4.4 Spare Cells

This command group handles spare cells in automatic metal ECO flow.

  • Create Spare Cells File

This command creates spare cells file.

  • Load Spare Cells File

This command loads the spare cells file created by the command above.

4.2.4.5 Launch Files Compare Window

This command launches netlist files compare window.

4.2.4.6 Process Timing Violations

This command launches Prime Time report file processing controller.

4.2.4.7 SDF

This command group handles SDF loading.

  • Create SDF Index File

This command creates SDF file index file. GOF doesn’t load the full SDF file, but SDF index file instead.

  • Load SDF Index File

This command loads SDF index file created by the command above.

4.2.5 Options Menu

4.2.5.1 Increase Font Size

This command increases the font size on the schematic.

4.2.5.2 Decrease Font Size

This command decreases the font size on the schematic.

4.2.5.3 Show Port

This option makes port name visible.

4.2.5.4 Show Wire

This option makes wire name visible.

4.2.5.5 Show Title

This option makes gate title visible.

4.2.5.6 Show Type

This option makes gate type visible.

4.2.5.7 Show Connections

This option makes wires visible.

4.2.5.8 Show Comment

This option makes comments visible.

4.2.5.9 Dump Waveform Restore File

This command pops up a window to setup simulation waveform restore file. Four waveform restore file formats are supported.

  • SimVision Restore File
  • ModelSim Restore File
  • Verdi Restore File
  • GtkWave Restore file

If one or more of the formats are selected, GofViewer and GofTrace pop menus have ‘Write Selected Nets to the Waveform Restore File’ as the first item, when a net is selected.

4.2.5.10 Save String to Clipboard

This option enables saving string to clipboard when a wire or instance name is clicked by mouse-left-button.

4.2.5.11 Cursor Mode

This is normal mode of the schematic tracing.

4.2.5.12 Line Edit Mode

This mode sets cursor in editing wire connections mode. Press mouse-left-button on the straight wire connection and move, the line is pulled by the cursor until the mouse button is released.

4.2.5.13 Setup

The command pops up configuration window for the tool setup.

4.2.6 Help Menu

4.2.6.1 General

General help information.

4.2.6.2 About

About Gates On the Fly.

4.2.6.3 nandigits.com/gof_manual.php

Visit the website for the manual.

4.2.7 Keyboard Shortcuts

4.2.7.1 Access Menu

Press key ‘Alt’ and underlined letter in menu.

4.2.7.2 Functions access

  • Ctrl-a: Select every object on the schematic
  • Ctrl-c: Copy the selected objects
  • Ctrl-v: Paste the content in clipboard copied by Ctrl-c
  • Ctrl-g: Load instance to schematic
  • Ctrl-w: Write to waveform dump restore file
  • Ctrl-x: Exit the current window
  • Ctrl-digit: Save the selection location as the digit indication, the schematic view moves the current saved location when the digit is pressed later

4.2.8 Selection Status

Click mouse-left-button on the schematic window, the object which can be net, instance under the cursor is highlighted. GofTrace pop menu has different content according to the selection status. Pressing keys Ctrl-a can have all selected on the schematic. Press mouse-left-button on empty space, and don’t release, move mouse down to select multiple objects.

4.2.9 GofTrace Pop Menu

Click mouse-right-button on GofTrace schematic, a menu pops up. The content of the menu varies as the selection status on the schematic.

4.2.9.1 Driver Until Non Buffer

Trace driver of an input pin. If the driver is a buffer or invert, the tracing will continue on the input pin of the buffer or invert, until the driver is non-buffer/invert. The feature can be used to trace the clock tree cells of a flop's clock input.

4.2.9.2 Drivers of Logic Cone

Logic Cone is the logic cluster between flops and ports, as shown in the following figure. Users should select the output flop or its pins to do logic cone extraction.

Figure 22: Logic Cone

  • On the Schematic

Draw the whole logic cone on the schematic.

  • In Text Mode

Display the whole logic cone in a pop up text window.

4.2.9.3 Copy Selected to

This command group does interactions between GofTrace windows and LayoutViewer windows.

  • Schematic New

Copy the selected items to a new schematic.

  • Schematic Number#

Copy the selected items to an existing schematic identified by ID Number.

  • Layout New

Copy the selected items to a new launched LayoutViewer window. The selected circuit is marked on the LayoutViewer window.

  • Layout Number#

Copy the selected items to an existing LayoutViewer window indentified by ID Number.

4.2.9.4 Nets Equivalence Check

The command needs Reference Netlist loaded.

  • Reference Netlist can be loaded by '-ref' option in command line. For example,
  • gof -lib tsmc.lib implementation.v -ref reference.v
  • Reference Netlist can be loaded by 'read_design' with '-ref' switch in GofCall script. For example,
  • read_design("-ref", "reference.v");

Use mouse-left-button to select on a pin in implementation netlist and press 'ctrl' key to click mouse-left-button on the other pin in reference netlist. So that one pin in implementation netlist and the other comparing pin in reference netlist are selected at the same time.

Click mouse-right-button to popup menu and select "Equivalence Check for 'neta' vs 'netb'" command.

Figure 23: Nets Equivalence Check

When the check is done, a pop window shows if the nets are equivalent.

4.2.9.5 Find Logic Equivalent Nets

Wire names in RTL codes are normally optimized away in synthesis process. GOF has a way to retrieve them. A reference netlist with the wire names preserved should be synthesized. There are several ways to preserve wire names.

  • Put the wires in output ports
  • Use 'preserve' or 'dont_touch' command in synthesis constraint file

Reference Netlist should be loaded with Implementation Netlist.

  • Reference Netlist can be loaded by '-ref' option in command line. For example, "gof -lib tsmc.lib implementation.v -ref reference.v"
  • Reference Netlist can be loaded by 'read_design' with '-ref' switch in GofCall script. For example, 'read_design("-ref", "reference.v")'

Start GUI Window, load the preserved wires on a schematic window. Select the pin that drives the wire, right click mouse-right-button to popup menu. Select 'List Logic Equivalent Nets of …' command.

Figure 24: List Logic Equivalent Nets

A popup window appears to list the nets that Logically Equal or Invert to the reference net. By popup menu on the window, the corresponding nets can be easily loaded into the schematic.

Figure 25: Logic Matching Nets

The feature is very convenient in manual ECO when the optimized wires have to be located in Implementation Netlist.

4.2.9.6 Find Circuit between Two Points

When two or more than two instances are selected on the schematic, the command item appears in the pop menu. This command finds the combination logic path between two instances.

4.2.9.7 Add Comments

This command adds comments entered by users on the schematic.

4.2.9.8 Find Gates on Schematic

This command pops up a window for users to enter a string to find the matching instances on the schematic. It matches portion of the full name. For example, ‘U’ matches ‘U0’, ‘U1’ and ‘U222’.

4.2.9.9 Find Nets on Schematic

This command pops up a window for users to enter a string to find the matching wires on the schematic. It matches portion of the full name. For example, ‘Net0’ matches ‘Net0’, ‘Net011’ and ‘Net023’.

4.2.9.10 Place and Route

This command group is to automatically place the gates on the schematic and automatically route the wires.

  • Auto Place and Route

This command is to do both placement and routing automatically.

  • Auto Place

This command is to do automatic placement only.

  • Auto Route

This command is to do automatic routing only.

  • Reset Route

This command is to reset all existing routes, all routed wires become straight.

4.2.9.11 Find selected in GofViewer

This command finds the selected instance back in GofViewer netlist window, and highlights the instance in the netlist window.

4.2.9.12 Edit Gate Display

This command pops up a window for users to add or change comments associated with the gate and change the color of the gate.

4.2.9.13 List Logic for the Selected Leaf Cell

This command pops up a text window to list the logic of the selected leaf cell.

4.2.9.14 List Context for the Selected Leaf Cell

This command pops up a text window to list the library content of the selected leaf cell. The content includes the cell’s pin definitions, area and timing.

4.2.9.15 List Definition for the Selected Instance

This command pops up a text window to list the instantiation of the selected instance.

4.2.9.16 Load Instance Similar to the Selected Instance

This command pops up an entry window with the current selected instance name pasted in the entry. So that user can do simple change to load other similar naming style instance onto the schematic.

4.2.9.17 Equivalent Symbol

This command changes the selected gate symbol display to the equivalent symbol according to DeMorgan's Laws. For example, NAND symbol is equivalent to Inputs Inverted OR symbol.

4.2.9.18 Delete

This command deletes the selected objects on the schematic. The object can be gates, wires and comments.

4.3 GofECO

GofECO uses the same window as GofTrace by enable ECO mode. The background color changes to light blue by default. The color can be configured by Menu Setup->GofECO->Color->BackGround. The ECO operation icons appear on the tool bar. GofECO uses the same menus GofTrace uses, besides the contents in ECO menu being activated.

Figure 26: GofECO Window

4.3.1 ECO Menu

4.3.1.1 Enable ECO and ECO Preferences

This option enable ECO mode, GofTrace switches to GofECO. A pop up window appears for inputting ECO setups.

Figure 27: ECO Preferences

  • ECO Name should be unique, so that name confliction can be avoided
  • ECO Header Comment is optional, which appears at the beginning of ECO netlist file
  • Checkbuttons 'Use Spares Only' and 'Map Spare gates' and 'Buffer Distance' entry are for Metal Only ECO. Their usages are:
  • Use Spares Only' is to use spare type gates only, a spare gate list file must be loaded with this option enabled.
  • Map Spare Gates' is to let the tool mapping any type gates to either the spare type gates or the exact spare instances in the design.
  • Buffer Distance' entry is to tell the tool add buffers/repeaters when the connection distance is larger than the limit. Inputting a large number can disable adding buffers. The corresponding script command is 'set_buffer_distance'.

4.3.1.2 Insert Gates

This command inserts gates in the selected wires. It requires one or more wires being selected on the schematic, before inserting gates. A ‘Gate selection’ window pops up for users to select proper type of gates and gate number. When multiple wires are selected and some wires have the same drivers, users can choose either one gate driving all shared wires or one gate driving each wire. Users are asked to choose the pin connections in ‘Specify pin connections’ window. The default pin connections setup can be used and users can modify the connections later on the schematic. Read this PDF use case for more detail.

gof_insert_buffers_inverters.pdf

4.3.1.3 Replace Gates

This command replaces the selected gates with a different type of gates. It requires one or more gates being selected on the schematic. If two or more than two gates are selected, they should have the same type. A ‘Gate selection’ window pops up for users to select proper type of gates to replace the selected ones. Users are asked to choose the pins connections in ‘Specify pin connections’ window. The default pin connections setup can be used and users can modify the connections later on the schematic.

4.3.1.4 Add Gates

This command adds new ECO gates on the schematic. A ‘Gate selection’ window pops up for users to select proper type of gate to add onto the schematic. The new ECO gates appear as output driving a new net and input floating. The hierarchy of the gate is undefined. When users connect one of the input pins to another existing gate or connect other gate’s floating input to the ECO gate’s output pin, the ECO gate gets the same hierarchy as the other gate. Read Add Connection for more detail.

4.3.1.5 Delete Selected Items

This command deletes the selected items. Users would be warned for deleting multiply objects at the same time.

4.3.1.6 Upsize Drive Strength

This command upsizes the selected gate to a higher drive strength gate with the same type. If there is no higher drive strength gate available, users would be warned with a pop up information window.

4.3.1.7 Downsize Drive Strength

This command downsizes the select gate to a lower drive strength gate with the same type. If there is no lower drive strength gate available, users would be warned with a pop up information window.

4.3.1.8 Undo ECO Operations

This command undoes the previous ECO operation, until no more ECO operation is in the pipeline.

4.3.1.9 Add Connection

There is no operation button/icon for Add Connection operation. Adding connection can only be done from a floating input pin to a output pin. User can press mouse-middle-button on a floating input pin, and don't release the mouse. Then move mouse to the destination output pin of the instance that user would like the wire connected to, release the button to make the connection to be created.

4.3.1.10 Save ECO

This command saves ECO result to a file. The supported file formats:

  • Verilog netlist
  • GofCall Perl Script
  • SOC Encounter ECO script
  • Tcl script for Synopsys
  • DC script for Synopsys

4.3.2 Metal Only ECO

Metal ECO only touches metal layers. Gates On the Fly provides four Metal Only ECO modes by combinations of setting up the options in ECO preference and loading DEF file.

4.3.2.1 Metal ECO, mode 1

User can add any type of gates and let the tool map to the spare type gates, Place and Route tool should map the spare type gates to the exact spare gate instances.

The setup for this mode:

  • Spare gate list file should be created and loaded.
  • DEF file should NOT be loaded.
  • 'Use Spares Only' is NOT checked.
  • 'Map Spare Gates' is checked.

A use case for Metal Only ECO mode 1 can be found in

gof_gui_metal_eco_mode_1.pdf

4.3.2.2 Metal ECO, mode 2

User can add any type of gates and let the tool map to the exact physically existing spare gate instances.

The setup for this mode:

  • Spare gate list file should be created and loaded.
  • DEF file should be loaded.
  • 'Use Spares Only' is NOT checked.
  • 'Map Spare Gates' is checked.

A use case for Metal Only ECO mode 2 can be found in

gof_gui_metal_eco_mode_2.pdf

4.3.2.3 Metal ECO, mode 3

User can add only spare type gates and let the tool map to the exact spare gate instances.

The setup for this mode:

  • Spare gate list file should be created and loaded.
  • DEF file should be loaded.
  • 'Use Spares Only' is checked.
  • 'Map Spare Gates' is checked.

 

A use case for Metal Only ECO mode 3 can be found in

gof_gui_metal_eco_mode_3.pdf

4.3.2.4 Metal ECO, mode 4

User can pick the exact spare gate instances, and connect and disconnect up the instances in ECO.

The setup for this mode:

  • Spare gate list file has no need to be created and loaded.
  • DEF file should be loaded.
  • 'Use Spares Only' is NOT checked.
  • 'Map Spare Gates' is NOT checked.

A use case for Metal Only ECO mode 4 can be found in

gof_gui_metal_eco_mode_4.pdf

4.4 LayoutViewer

 

LayoutViewer window displays partial physical placements. The circuit drawn on the schematic can be highlighted on LayoutViewer. It has full interactivity with GofTrace. It requires physical design files including DEF and LEF files to be loaded.

Figure 28: LayoutViewer Window

4.4.1 File Menu

4.4.1.1 Capture in PDF

This command captures the current LayoutViewer display to PDF file. PDF is only supported in Linux Platform. In Windows Platform, the captured display is saved in PostScript format.

4.4.1.2 Exit

Exit LayoutViewer.

4.4.2 Commands Menu

4.4.2.1 Clear Circuit Markers

Clear circuit markers which can be created by Drag-And-Drop from GofTrace Partial Schematic.

4.4.2.2 Clear Search Markers

Clear search markers which are those highlighted cells matching the searching string in search entry.

4.4.2.3 New Schematic

When cells or markers are selected in LayoutViewer, this command can launch a schematic with selected instances on it.

4.4.3 OptionsMenu

4.4.3.1 Show Grid

This option shows grid on LayoutViewer.

4.4.3.2 Show Instance

This option shows instance name on LayoutViewer. Zoom in scale should be large enough to show instance names.

4.4.3.3 Show Module

This option shows module name on LayoutViewer. Zoom in scale should be large enough to show module names.

4.4.3.4 Setup

LayoutViewer setups which include maximum search matching number and placement display zone area size.

4.4.4 Help Menu

4.4.4.1 Help on LayoutViewer

Visit NanDigits web site for Gates On the Fly manual section LayoutViewer.

4.4.5 LayoutViewer Pop Menu

Click mouse-right-button to pop up the menu.

4.4.5.1 Clear Circuit Markers

Clear circuit markers which can be created by Drag-And-Drop from GofTrace Partial Schematic .

4.4.5.2 Clear Searching Markers

This command clears searching markers which were activated by search function.

4.4.5.3 Copy Selected to

This command copies the selected gates to the following destination:

  • Back to GofViewer
  • A new Schematic
  • An existing Schematic indentified by Number ID

4.4.6 Keyboard and mouse combination

4.4.6.1 Ctrl key to measure length

Press 'Ctrl' key and move mouse, the Cursor Coordination displays the length cursor moves in unit of 'um'.

4.4.6.2 Shift key to select multiple markers

Press 'Shift' key and press mouse-left-button, move mouse to draw a virtual rectangle. When release the mouse-left-button, those markers in the virtual rectangle are all highlighted. Click mouse-right-button to pop menu, those selected instances can be sent to other schematics or GofViewer the netlist view window by 'Copy Selected to' command.

4.4.7 Mouse operations

  • Mouse-middle-wheel: Roll up to zoom in and roll down to zoom out the LayoutViewer window.
  • Mouse-left-button: Click and release to select cells or markers. Press on LayoutViewer window to move it around.
  • Mouse-middle-button: Drag-And-Drop selected instances.
  • Mouse-right-button: Release to pop up menu.

4.4.8 Select color buttons

Click color buttons in 'Select color:' bar to select the current color. 'Select Color:' string changes to the current selected color. Any new Circuit Markers and Search Markers have this color.

4.4.9 Search function

Type search string in Search Entry to highlight the leaf instances matching the string on the LayoutViewer. The search string is in 'path/instance' string format, separated by '/'. Wildcard can be used in path and instance names. The markers have the color selected in 'Select color' bar.

The search string takes these options:

  • -spare: When spare gate list is loaded by -sparelist option or get_spare_cells command.
  • -type type-name: Only search those instances with specified type, 'nand' for example.
  • -hier: Search all leaf instances under the specified hierarchy. For example, 'u_clk/* -hier'.
  • -ref ref-name: Only search those instances with specified reference, 'NAND2X2' for example.

Examples:

'u_rtc/*' : Search leaf instances in hierarchy 'u_rtc'.
'* -hier -type nand': Search all leaf instances with 'nand' type in the design.
'u_clk/* -hier': Search all leaf in hierarchy 'u_clk' and its sub-hierarchies.

 

5 Appendix A

5.1 GOF Command Options

Usage: gof [options] netlists
netlists
   Netlist files to be loaded. There can be multiple netlist files listed,
   if the design has more than one netlist files.
options:
-h
   Print out this info.

-lib
   Provides liberty file (technology library).
   There can be multiple -lib options,
   if the design has more than one technology library files.

-v
   Specifies simulation library file name which has verilog definition
   for leaf gates, like AND2X4.
   There can be multiple -v options, if the design has more than one simulation library.
    -lib should be used unless the leaf cells defined in simulation library are true black box

-vmacro
   For ECO purpose. Each module in the file appears as leaf cell, and it can be
   added like other leaf cell in ECO. When write out ECO netlist, the file content appears
   in the beginning of ECO netlist. And the ECO cell is added as a hierarchical sub-block.
   
-run
   Provides ECO script name. The script is compatible with Perl syntax.
   GOF stays in shell mode when the script finishes.

-shell
   Runs in text mode with shell prompt, GofCall APIs can be run in interactive mode in shell.

-o
   Specifies log file name, default gatesof.log.

-Top_1
   Specifies another netlist files to build Top_1 tree. The hierarchy will shown up in left
   side of GofViewer window. -Top_2 -Top_3 ... can be used to load more netlist files.
   Note, when this option takes all netlist files followed, so the main netlist files
   should appear before this option. For example,
   'gof -lib tsmc.lib imp_netlist1 imp_netlist2 -Top_1 ref_netlist1 ref_netlist2'
   will create two trees in the left side of GofViewer window.
   While, 'gof -lib tsmc.lib -Top_1 imp_netlist1 imp_netlist2 ref_netlist1 ref_netlist2'
   will build only one tree, since Top_1 option takes up all of the netlist files,
   the main tree is gone.
   
-ref
   Specifies reference netlist files.
   +define+PARAMETER0+PARAMETER1
   Defines PARAMETER0 PARAMETER1.
   
-id
   Specifies design name. The name appears on GUI Window tile bar.
   
-def
   Specifies DEF file (Design Exchange Format).
   There can be multiple -def options,
   if the design has more than one def files.

-defverbose
   Reports all def error, otherwise only first 10 are reported.
   
-lef
   Specifies Library Exchange Format file.
   There can be multiple -lef options,
   if the design has more than one lef files.

-sparelist
   Specifies spare cells list file.
   
-parallel
   Define parallel processing CPU Core number.
   Set the number to zero to disable parallel processing.
   By default, the tool picks a optimal number according to the host CPU setting.

-f
   Loads all the files and options in the file_list_file
   
-vcd
   Specifies VCD file for schematic annotation
   
-textbutton
   Text mode button instead of image mode button in ECO operations
   
-version
   Prints out current version and exits.
   
-licquery
   Queries license usage.

 

5.2 Command line Examples

gof -lib tsmc.lib soc.v
   Loads one netlist file 'soc.v' and one technology library, 'tsmc.lib'
gof -lib tsmc_std.lib -lib tsmc_io.lib top.v part0.v part1.v
   Loads three netlists, top.v, part0.v and part1.v, two liberty files
   tsmc_std.lib, IO cells, tsmc_io.lib
gof -lib tsmc_std.lib -lib tsmc_io.lib -v analog_models.v top.v part0.v part1.v
   Loads analog cells in verilog library file analog_models.v all analog cells are black boxes.
gof -lib tsmc_std.lib -lib tsmc_io.lib -vn macros.v -v analog_models.v top.v part0.v part1.v
   Loads macros.v as macro cell
gof -lib tsmc.lib -def soc.def.gz -lef libcell.lef soc.v
   Loads Design Exchange Format file soc.def.gz. And library exchange format file for layout view usage.
gof -lib tsmc.lib soc.v -run scripts.pl
   Processes netlist with scripts.pl. Scripts.pl is in Perl syntax and support GOF APIs
gof -lib tsmc.lib top.v netlist.vg -vcd top.vcd
   Loads VCD file for schematic annotation.
gof -lib tsmc.lib imp_netlist.v -ref ref_netlist.v
   Loads both implementation netlist and reference netlist, can be used in netlist comparison.
 

6 Appendix B

 

6.1 Fatal codes

F-000: License failed
F-001: Time out in adding ports in hierarchies
F-002: Empty ID for nets
F-003: Pin connections processing fatal error
F-004: Net id not defined
F-005: Net is not in EpHash
F-006: Instance has not been mapped position in AUTO ECO
F-007: Instance has no name mapping in AUTO ECO
F-008: No net found for ECO instance/pin
F-009: Unknown connection type of instance/pin in AUTO ECO
F-010: Net has no name mapping in AUTO ECO
F-011: Failed to initialize database
F-012: MCell get sub-chains error
F-013: No tree has been defined
F-014: No ID for leaf cell pin
F-015: Undefined subroutine in GofCall script
F-016: Global symbol requires explicit package name
F-017: Syntax Error
F-018: Illegal Division by zero
F-019: Bare word not allowed
F-020: Can't locate Perl module
F-021: File size too large for evaluation mode
F-022: Internal error in make miss

6.2 Error codes

E-001: Reference netlist has not been loaded
E-002: DEF file has missing section
E-003: Command line needs an option for a switch
E-004: Liberty files have not been loaded
E-005: Library cell doesn't exist
E-006: Delete middle bit in a bus
E-007: Unknown command line option
E-008: Win32 doesn't support .gz file
E-009: DEF file doesn't have DIEAREA item
E-010: Files loading sequence
E-011: Instance or pin or port can't be found in module
E-012: Net doesn't exists in module
E-013: Tree name doesn't exist
E-014: Hierarchical module name doesn't exist
E-015: Miss argument
E-016: Module stack is empty, too many pop_top
E-017: 'instance/pin' has wrong format
E-018: Instance or module doesn't exist
E-019: Instance doesn't have pin
E-020: Item is a black box
E-021: Missing DEF file
E-022: No reference for instance
E-023: 'leaf/pin' doesn't exist
E-024: Power connection format is wrong
E-025: Spare cell pattern is not specified
E-026: Spare list file doesn't exist
E-027: 'get_spare_cells' run before 'map_spare_cells'
E-028: 'instance/pin' is floating
E-029: New instance conflicts with existing one
E-030: Specify leaf:num in more than one output leaf
E-031: Instance should be leaf in change_gate
E-032: Syntax error in pin mapping
E-033: The new gate type should be different from the old one in change_gate
E-034: Leaf cell doesn't exist in libraries
E-035: Net doesn't have a driver
E-036: Instance name has special character that the tool doesn't support
E-037: Wrong argument in ECO APIs
E-038: Net has multiple drivers
E-039: Not a port
E-040: New port conflicts with existing one
E-041: Single bit wire can't be expanded to a bus
E-042: New port direction conflicts with existing one
E-043: Commands loading sequence
E-044: Nets in one ECO command should be in the same hierarchy
E-045: Missing scan control pins
E-046: Reference netlist is not loaded
E-047: Fail to open file for write
E-048: Fail to open file for read
E-049: Unable to recognize file format
E-050: Command line option needs a value
E-051: Path doesn't exist
E-052: Leaf should have only one output pin
E-053: New net conflicts with existing one
E-054: Instance ECO result not consistent
E-056: Net has no driver
E-057: Net has invalid BDD
E-059: Not enough resource to run synthesis
E-060: Not valid patch file
E-061: No spare cell for one gate type
E-062: Output port is driven by input port
E-063: Reference register doesn't exist in implementation netlist
E-064: No inverter in the database
E-067: Should add instance into fix_logic argument
E-071: Port doesn't exist in hierarchical instance
E-072: Black box instance doesn't exist in implementation netlist in AUTO ECO
E-076: Spare cells list file has Wrong format
E-080: GOF_KEY_FILE variable has not been defined
E-081: Use '-run' to run Perl script
E-082: Gtech file doesn't exist
E-085: Syntax error in netlist
E-101: No hierarchical path is used
E-102: Interrupt GUI operation by user
E-103: 'read_def' should be run before 'get_spare_cells'
E-105: Load specific file without the right option
E-106: Source ID can't be deleted
E-109: Found combinational loop
E-110: Implementation Netlist has not been loaded
E-112: Can't find pin direction

6.3 Warning codes

W-001: Bypass already loaded file
W-002: DEF has some section missing
W-003: DEF has module not resolved
W-004: No ECO pin specified for ECO instance
W-005: Not enough spare cells
W-006: DEF file not loaded
W-007: Leaf cell doesn't have timing table
W-023: 'leaf/pin' doesn't exist
W-028: 'instance/pin' is floating
W-038: Net has multiple drivers
W-054: Instance ECO result not consistent
W-055: Net ECO result not consistent
W-056: Net is not driven
W-060: Invalid patch file
W-061: No spare cell for one gate type
W-065: Tie floating input pin to zero
W-066: New port created in AUTO ECO
W-068: Hierarchical cell is created in AUTO ECO
W-069: Set don't touch Warning
W-070: Can't find repeaters
W-073: 'instance/pin' is inverted but being forced to be equal by user
W-074: 'instance/pin' is forced to be inverted by user
W-075: Net returned wrong BDD
W-077: No size information for a leaf
W-078: Module is redefined
W-079: Instance can't be resolved in GTECH
W-080: Leaf cell can't be resolved in module
W-083: Can't read MAC Address
W-084: Sub-module can't be resolved
W-086: Include file doesn't exist
W-087: Bit-width mismatch in instantiation
W-088: Zero fanin endpoint
W-089: Can't find ECO instance position
W-090: Empty instance name in patch file
W-091: ECO net has no fanout
W-092: New input port created and needs to be connected
W-093: New ID created for end point
W-094: Can't detect port phase in module
W-095: Port or net is forced to be equal by user
W-096: Port and net has mismatching bit-width
W-097: Schematic only feature
W-098: Force to use 1'b0/1'b1 in AUTO ECO
W-099: Can't fix timing, since lacking valid points
W-100: No lib name for a leaf cell
W-104: Module is defined as leaf cell but has definition in the netlist
W-107: Module is set as a leaf by user
W-108: Module is not uniquified
W-111: No need to set path prefix
W-112: Can't find pin direction
W-113: Different types of flops in IMP and REF

6.4 GUI warning codes

GW-001: Don't connect net to a new created connector
GW-002: Don't connect two ECO connectors
GW-003: Don't drive an output port by a cell in different hierarchy in ECO
GW-004: Forward trace a port's driver before insertion
GW-005: Net doesn't exist in design
GW-006: Can't load cell to schematic
GW-007: Trace output pin before delete the gate
GW-008: Can't delete a gate which drives an output port
GW-009: Can't delete a wire which drives an output port
GW-010: Need select a gate to do a operation
GW-011: Can't change ECO gate size
GW-012: No larger size gate in library
GW-013: No smaller size gate in library
GW-014: Connect other side of ECO port first
GW-015: Path is not allowed in port connection
GW-016: Can't disable ECO mode
GW-017: No more ECO operations in undo
GW-018: Need select a pin to do listing endpoints
 

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