RTL to RTL Supplemental ECO Flow

Overview

RTL to RTL comparison is the supplemental process for the netlist ECO flow. The post-layout netlist under ECO has DFT logic inserted and boundary optimization which create complexities for Gate to Gate comparison and it slows down the ECO process and may bring redundant ECO fixes in the patch generation. RTL to RTL comparison is faster and more focused comparing with Gate to Gate equivalence checker.

As shown in the Figure 1, RTL to RTL comparison is running in parallel with the key-point mapping of two gate level netlists. Gate to Gate comparison will be bypassed if the non-equivalent points found by RTL to RTL comparison have been successfully integrated into the main ECO flow.

Figure 1: RTL to RTL Supplemental ECO Flow

Files and data requirements

Steps to do RTL to RTL supplemental ECO

RTL to RTL ECO example script

The GofCall script has exact the same syntax of Perl script. It runs the exported APIs that access the netlist database and modify the netlist.

The following is the example script for RTL to RTL supplemental ECO:

# GofCall ECO script, run_example.pl
use strict;
undo_eco; # Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
my $rtl2rtl = 1;
if($rtl2rtl){
  set_define("SYNTHESIS");
  set_define("NO_SIM");
  set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include");
  read_rtl('-ref', "ref0.sv", "ref1.sv", "ref2.sv");
  read_rtl('-imp', "imp0.sv", "imp1.sv", "imp2.sv");
  set_top("topmod");
  rtl_compare;
}
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
# Preserve DFT Test Logic
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
save_session("current_eco_name"); # Save a session for future restoration
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

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