RTL Guided ECO Flow

Overview

The RTL Guided ECO Flow is an additional step in the netlist ECO process, which involves comparing RTL designs to identify any discrepancies. Unlike Gate to Gate comparison, this method is faster and more targeted. The ECO process can be slowed down by the insertion of DFT logic and boundary optimization, making gate-to-gate comparison more complicated. Additionally, the use of RTL comparison can prevent the generation of redundant ECO fixes during patch generation.

Figure 1 illustrates how RTL to RTL comparison runs parallel to the key-point mapping of two gate-level netlists. If the non-equivalent points identified by RTL comparison have been integrated into the ECO flow successfully, gate-to-gate comparison can be bypassed.

Figure 1: RTL Guided ECO Flow

Files and data requirements

• Liberty files with extension '.lib'
• Other Verilog libraries files for modules not covered in '.lib' files
• Implementation SVF and Reference SVF file, optional
• Implementation Netlist on which ECO will be done
• Reference Netlist synthesized with the same constraints as the pre-layout netlist
• Implementation RTL which is logically equivalent to the Implementation Netlist
• Reference RTL which is logically equivalent to the Reference Netlist
• The top level module name under ECO

Steps to do RTL guided ECO

• Modify the original RTL
• Synthesize the new RTL to get Reference Netlist
• Create GofCall ECO script:
  • Specify ECO name in 'setup_eco'
  • Load Liberty files and Verilog libraries
  • Load Reference RTL (the modified RTL) and Implementation RTL (the original RTL)
  • Check non-equivalent points by 'rtl_compare'
  • Load Reference Netlist and Implementation Netlist
  • Fix the design by 'fix_design'
  • Report ECO status and write out ECO results
• Run the above ECO script

RTL guided ECO example script

The GofCall script has the exact same syntax as Perl script and runs the exported APIs that access the netlist database and modify the netlist.

The following is the example script for RTL guided ECO:

# GofCall ECO script, rtl_guided.pl
use strict;
undo_eco; # Discard previous ECO operations
setup_eco("rtl_guided_eco_example");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
my $rtl2rtl = 1;
if($rtl2rtl){
  set_define("SYNTHESIS");
  set_define("NO_SIM");
  set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include");
  read_rtl('-ref', "ref0.sv", "ref1.sv", "ref2.sv");
  read_rtl('-imp', "imp0.sv", "imp1.sv", "imp2.sv");
  set_top("topmod");
  rtl_compare;
}
read_svf("-ref", "reference.svf.txt");       # Optional, must be loaded before read_design, must be in text format\n";
read_svf("-imp", "implementation.svf.txt");  # Optional, must be loaded before read_design, must be in text format\n";
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
# Preserve DFT Test Logic
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
save_session("current_eco_name"); # Save a session for future restoration
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

Synthesize Reference RTL to Reference Netlist

If Reference Netlist is not provided, it can be synthesized from Reference RTL by 'synthesize' command.

As shown in Figure 2, Reference RTL is directly synthesized into Reference Netlist and used in the ECO.

Figure 2: RTL Guided ECO Flow

The following is the example script for Reference RTL synthesis in RTL guided ECO:

# GofCall ECO script, rtl_guided_synthesis.pl
use strict;
undo_eco; # Discard previous ECO operations
setup_eco("rtl_guided_eco_example");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
set_define("SYNTHESIS");
set_define("NO_SIM");
set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include");
read_rtl('-ref', "ref0.sv", "ref1.sv", "ref2.sv");
read_rtl('-imp', "imp0.sv", "imp1.sv", "imp2.sv");
set_top("topmod");
rtl_compare;

read_svf("-imp", "implementation.svf.txt");  # Optional, must be loaded before read_design, must be in text format\n";
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
elaborate; # The command synthesizes the Reference RTL to Reference Netlist 
# Preserve DFT Test Logic
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
save_session("current_eco_name"); # Save a session for future restoration
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears