RTL to RTL supplemental ECO flow

RTL Guided ECO Flow

RTL-guided ECO employs two approaches: utilizing the built-in RTL logic equivalence checking engine of GOF or incorporating results from third-party LEC tools to pinpoint areas needing ECO adjustments. The advantage of the internal RTL LEC is its speed and efficiency. However, a drawback arises when hierarchies mismatch with synthesized netlists, particularly in designs with extensive SystemVerilog statements. To address this, third-party RTL LEC tool results can be utilized to resolve hierarchy inconsistencies. For example, GOF ECO can process a list file of non-equivalent results from tools like Synopsys Formality, allowing it to concentrate ECO efforts solely on identified areas.

Internal RTL to RTL Guidance

The RTL Guided ECO Flow is an additional step in the netlist ECO process, which involves comparing RTL designs to identify any discrepancies. Unlike Gate to Gate comparison, this method is faster and more targeted. The ECO process can be slowed down by the insertion of DFT logic and boundary optimization, making gate-to-gate comparison more complicated. Additionally, the use of RTL comparison can prevent the generation of redundant ECO fixes during patch generation.

Figure 1 illustrates how RTL to RTL comparison runs parallel to the key-point mapping of two gate-level netlists. If the non-equivalent points identified by RTL comparison have been integrated into the ECO flow successfully, gate-to-gate comparison can be bypassed.

Figure 1: RTL Guided ECO Flow

Files and data requirements in RTL guided ECO

Liberty files with extension '.lib'
Other Verilog libraries files for modules not covered in '.lib' files
Implementation SVF and Reference SVF file, required for designs with multibit flops
Implementation Netlist on which ECO will be done
Reference Netlist synthesized with the same constraints as the pre-layout netlist
Implementation RTL which is logically equivalent to the Implementation Netlist
Reference RTL which is logically equivalent to the Reference Netlist
The top level module name under ECO

Steps to do RTL guided ECO

Modify the original RTL
Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist
Create GOF ECO script:
- Specify ECO name in 'setup_eco'
- Load Liberty files and Verilog libraries
- Load Reference RTL (the modified RTL) and Implementation RTL (the original RTL)
- Check non-equivalent points by 'rtl_compare'
- Load the Reference Netlist and the Implementation Netlist
- Fix the design by 'fix_design'
- Report ECO status and write out ECO results
Run the above ECO script by "gof -run eco_script.pl"

RTL guided ECO example script

GOF script has the exact same syntax as Perl script and runs the exported APIs that access the netlist database and modify the netlist.

The following is the example script for RTL guided ECO:

# GOF ECO script, rtl_guided.pl
use strict;
setup_eco("rtl_guided_eco_example");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
my $rtl2rtl = 1;
if($rtl2rtl){
  set_define("SYNTHESIS");
  set_define("NO_SIM");
  set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include");
  read_rtl('-ref', "ref0.sv", "ref1.sv", "ref2.sv");
  read_rtl('-imp', "imp0.sv", "imp1.sv", "imp2.sv");
  set_top("topmod");
  rtl_compare;
}
read_svf("-ref", "reference.svf.txt");       # Optional, must be loaded before read_design, must be in text format
read_svf("-imp", "implementation.svf.txt");  # Optional, must be loaded before read_design, must be in text format
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
# Preserve DFT Test Logic
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
save_session("current_eco_name"); # Save a session for future restoration
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

Synthesize Reference RTL to Reference Netlist

If Reference Netlist is not provided, it can be synthesized from Reference RTL by 'synthesize' command.

As shown in Figure 2, Reference RTL is directly synthesized into Reference Netlist and used in the ECO.

Figure 2: RTL Guided ECO Flow

The following is the example script for Reference RTL synthesis in RTL guided ECO:

# GOF ECO script, rtl_guided_synthesis.pl
use strict;
setup_eco("rtl_guided_eco_example");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
set_define("SYNTHESIS");
set_define("NO_SIM");
set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include");
read_rtl('-ref', "ref0.sv", "ref1.sv", "ref2.sv");
read_rtl('-imp', "imp0.sv", "imp1.sv", "imp2.sv");
set_top("topmod");
rtl_compare;

read_svf("-imp", "implementation.svf.txt");  # Optional, must be loaded before read_design, must be in text format
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
elaborate; # The command synthesizes the Reference RTL to Reference Netlist 
# Preserve DFT Test Logic
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
save_session("current_eco_name"); # Save a session for future restoration
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

Third Party RTL LEC Result Processing

GOF ECO has the capability to ingest a list of ECO points, enabling it to concentrate exclusively on the items specified in the list. The format of the list file comprises a type designation followed by one or multiple spaces and then the non-equivalence point.

inst yak_zcvg_inst/skip_pix_reg
port te_coord[5]
inst yak_hah_inst/x_start_pa_reg_31_
inst yak_hah_inst/x_end_pa_reg_30_
inst yak_hah_inst/x_end_pa_reg_29_
inst yak_hah_inst/x_end_pa_reg_28_
inst yak_hah_inst/x_end_pa_reg_27_
inst yak_hah_inst/x_end_pa_reg_26_
pin yak_hah_inst/u_sync_cell/D

The ECO list file is incorporated using the '-list_file' option within the 'read_design' command. It can be generated from a Third Party LEC non-equivalence result file. For instance, in Synopsys Formality, the command 'report_failing_points > formality_non_eq.report' generates such a file. In a GOF ECO script, this report file is then read in and converted into the list file.

Below is an example script demonstrating the conversion of Third Party LEC results and execution of GOF ECO with the 'list_file' option:

use strict;
my $list_cont = "";
open(FIN, "formality_non_eq.report");
while(<FIN>){
  if(m/Ref\s+(\w+)\s+r:\/\w+\/\w+\/(.+)/){
    my $fm_type = $1;
    my $point = $2;
    my $gof_type = "inst";
    if($fm_type =~ m/Pin/){
      $gof_type = "pin";
    }elsif($fm_type =~ m/Port/){
      $gof_type = "port";
    }else{
      # For instance type
      $point =~ s/\[/_/g; # Mostly abc_reg[0] has name changed to abc_reg_0_ in the netlist
      $point =~ s/\]/_/g;
    }
    $list_cont .= "$gof_type $point\n";
  }
}
close(FIN);
open(FOUT, ">eco_list.txt");
print FOUT $list_cont;
setup_eco("eco_list_file"); # Setup ECO name
set_log_file("eco_list_file.log");
read_library("tsmc.5nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP");
set_pin_constant("test_mode", 0);
set_pin_constant("scan_en", 0);
set_ignore_output("test_so*");
fix_design("-list_file", "eco_list.txt"); # -list_file option to read in the ECO list file with the ECO points
report_eco();
write_verilog("eco_verilog.v");
exit;