Gate level simulation flow
More and more design companies require enough gate level simulation (GLS) coverage before chip tapeout. Even though sophisticated STA tool and logic equivalence check tool have been run on the netlist, but there are still coverage holes. For example, logic equivalence tool doesn't cover X optimism and STA tool may have wrong constraints.
However, gate level simulation is much harder than RTL level simulation. The main difficulties are:
- X propagations caused be X pessimism
- X source tracing and debug is very time consuming
- Post-layout boundary optimization makes debug even harder
Gates On the Fly provides unique and practical solutions to handle these difficulties.
1. Solution to Suppress X Propagations
'X' propagation in GLS is mostly caused by 'X' pessimism, so it is practical to suppress them and focus on the main purpose of GLS.
GOF provides a script flow to suppress most of 'X' propagations in GLS.
2. Solution for X Source Tracing
Even most of the 'X' propagations can be suppressed by solution 1, user may still need to debug other 'X' propagations.
GOF communicates to waveform tool through TCP/IP link. The incremental schematic engine becomes a powerful X source tracing tool.
3. Solution for Boundary Optimization Debug
In Place & Route stage, backend tool may change a port's phase. So a bus port name is the same in post-layout netlist, but logic wise, one or more of the bus bits may have been inverted caused by inverter moved across hierarchy boundary. This boundary optimization process may cause mismatches in gate level simulation.
GOF has unique Logic Equivalence Check feature to handle Boundary optimization debug