## Clock Gating Cell or MUX

Using clock gating in logic design can save area and reduce power when the grouped number of flops is larger than a threshold which is calculated by the area ratio of MUX and clock gating cell. Clock gating logic can be converted to MUX feedback format as shown in the Figure 1. When the area of clock gating cell is less than area of MUX multiplying flop number, it's area saving to use clock gating logic.

**Figure 1: Clock Gating vs MUX**

In gate array spare cell ECO, when more than three flops using one clock gating, it is more area saving than MUX logic. According to the table of tile numbers used in gate array cells, the left clock gating logic in the Figure 1 occupies 32 tiles (5X4+12), while the right MUX logic uses 40 tiles (5X4+5X4). So four flops group using clock gating cell can save 8 tiles.

Tile Numbers | Spare Cells | Functional Cells |
---|---|---|

1 | GFILL1 | GTIE GINVD1 GND2D1 GNR2D1 |

2 | GFILL2 | GBUFD1 GAN2D1 GOR2D1 GAOI21D1 GDN3D1 |

3 | GFILL3 | GAO21D1 GAN4D1 GOR4D1 |

4 | GFILL4 | GINVD8 GAN2D4 |

5 | GFILL5 | GMUX2D1 GXOR2D1 GXNOR2D1 |

6 | GFILL6 | GBUFD8 GSDFFRQD1 GSDFFSQD1 |

8 | GFILL8 | GINVD16 |

12 | GFILL12 | GCKLNQD6 |

**Table: Gate Array Tiles Number for Cells**

However the case becomes more complicated when the gates are mapped to real gate array spare fillers. Because clock gating cell uses 12 tiles, it has much less distribution than 5-tiles MUX. In the Figure 2, the 12-tiles filler found is relatively far from the flops and it affects timing closure.

**Figure 2: Placement for One Clock Gating Cell Drives Four Flops**

While the MUX logic has much more resources to find close-by 5-tiles MUXs, so the placement is much more concentrated and connections are much shorter. So it is practical to select MUX logic in stead of clock gating logic in this case.

**Figure 3: Placement for Four MUXs Drive Four Flops**

GOF has API convert_gated_clocks to convert clock gating logic to MUX feedback format logic. Visit the User Manual for more detail.