The Full Layers Functional ECO allows for the addition or removal of gates in a flexible manner. The ECO operations are performed using a script in Perl syntax, which accesses, modifies, and saves the netlist database using exported APIs. GOF ECO reads in two netlist files: the Implementation Netlist (which is under ECO) and the Reference Netlist (which is re-synthesized from modified RTL with the same constraints as the pre-layout netlist). In the ECO script, the 'fix_design' API is used to fix the top-level module and its sub-modules in global mode. GOF utilizes its built-in Logic Equivalent Check Engine to identify non-equivalent points and applies optimized minimum size gate patches to fix the non-equivalent modules.
Figure 1 shows that two logic cones are extracted from the Implementation and Reference Netlist for the same comparison point. Initially, the implementation point does not match the reference point. GOF compares the two points and generates a patch from the Reference logic cone, which it applies to the Implementation Netlist. After patching, the two points become equivalent.
Figure 1: Logic Cone Optimization
GOF performs logic cone analysis and optimization for each failing point discovered during top-down logic equivalence checks. The failing point takes the form of an output port or input pin of a sequential element, such as a flip-flop's D input. The final patch contains the fewest number of gates required to ensure that the implementation logic cone matches the reference logic cone.
Figure 2 depicts the flow chart of the process.
Figure 2: Automatic functional ECO flow
Steps for an automatic functional ECO:
The ECO script has exact the same syntax of Perl script. It runs the exported APIs that access the netlist database and modify the netlist.
The following is the example script for automatic functional ECO:
# GofCall ECO script, run_example.pl use strict; undo_eco; # Discard previous ECO operations setup_eco("eco_example");# Setup ECO name read_library("art.5nm.lib");# Read in standard library read_svf("-ref", "reference.svf.txt"); # Optional, must be loaded before read_design, must be in text format\n"; read_svf("-imp", "implementation.svf.txt"); # Optional, must be loaded before read_design, must be in text format\n"; read_design("-ref", "reference.gv");# Read in Reference Netlist read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO set_top("topmod");# Set the top module # Preserve DFT Test Logic set_ignore_output("scan_out*"); set_pin_constant("scan_enable", 0); set_pin_constant("scan_mode", 0); fix_design; save_session("current_eco_name"); # Save a session for future restoration report_eco(); # ECO report check_design("-eco");# Check if the ECO causes any issue, like floating write_verilog("eco_verilog.v");# Write out ECO result in Verilog exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears
When working with designs that include multibit flops or significant name changes, SVF files can be a valuable tool for facilitating key point mapping. Although multibit flops are used to reduce silicon area and power consumption, the different combinations of single bit flop instances in each multibit flop instance can create challenges for key point mapping, especially when combined with name changes. Additionally, backend tools may split or merge multibit flops, further complicating the process. To avoid these challenges and ensure accurate key point mapping, it's highly recommended to load SVF files when working with multibit flops. For more information on this topic, please refer to the Multibit Flops in ECO section.
The ECO Script can be run by '-run' option.
Check Run and debug ECO script section in User Manual for more detail
The example is in the released package.
To run the example:
The log file shows there are total 35 gates in the initial logic cone. After optimization, the patch has only 1 complex cell and 8 inverts