GOF uses internal synthesis engine or external synthesis tool to map patch logic to spare gates. The spare gate list requires one or both of the following spare type combinations.
In the Figure 1, the circuit generated by ECO in the left side has random standard cells. The mapping process maps the MUX and flop type gates directly to the spare gates, since they have one to one matching gate in the spare gate list. For the complicated cell type AO32, it has to be synthesized and mapped to 3 AND gates and one NOR gate.
Figure 1: Standard Cells Spare Gates Mapping
Check Standard Cells Metal Only ECO for detail