Standard Cells Spare Gates Mapping

GOF employs an internal synthesis engine to map patch logic onto spare gates. These spare gates must consist of the following spare type combinations.

1. Two ports 'and/or' gates, 'inv' gates and flops, 'mux' is optional.
2. Two ports 'nand/nor' gates, 'inv' gates and flops, 'mux' is optional.
3. Two ports 'nand/nor/and/or' gates, 'inv' gates and flops, 'mux' is optional.

Out of the three combinations, the second combination has the least area and the third combination has the best performance in metal only EOC.

In Figure 1, the circuit produced by ECO on the left-hand side contains arbitrary standard cells. During the mapping process, gates of type MUX and flop are mapped directly onto the spare gates, as they have a one-to-one correspondence with the spare gate list. However, for more complex cell types such as AO32, they must be synthesized and mapped onto three AND gates and one NOR gate.

Figure 1: Standard Cells Spare Gates Mapping

Check Standard Cells Metal Only ECO for detail