DFT Friendly ECO

During functional ECO, DFT should be configured to be in inactive mode. Any functional changes are not supposed to affect DFT logic. However, some ECOs may affect DFT logic when the changes involve DFT paths.

ECO insertion in back to back flops

The following partial scan chain is valid from A_REG to D_REG. B_REG is C_REG are back to back path and C_REG is good to be non-scan flop.

Figure 1: Scan Chain with back to back flops

A functional ECO inserts combinational logic between B_REG and C_REG and it breaks DFT function if the scan chain is not fixed.As shown in Figure 2, the scan chain is broken. Cadence Conformal ECO breaks this type of ECO by directly insert logic in the back to back path without fixing scan chain.

Figure 2: ECO inserts logic into back to back path

The right solution of GOF is to change C_REG flop type to scan flop and connect up the scan chain, as shown in Figure 3.

Figure 3: GOF fixes the DFT logic by reconnecting up the Scan Chain

Pick the right signal for DFT

DFT_MODE is set to zero to force DFT logic in inactive mode. During functional ECO, some nets are equivalent but some are good for DFT, the others would break DFT. For example, as shown in Figure 4 an ECO needs to pick one signal from two equivalent signals mux_in or mux_out to drive a flop's reset pin. Cadence Conformal ECO picks mux_in which breaks DFT. GOF can detect the presence of the MUX and pick mux_out as the right signal to drive the flop's reset pin.

Figure 4: Pick the right signal to maintain DFT logic

Set reset flop swapping

Changing flops between settable and resettable types should not break DFT function. GOF makes direct flop type change in the ECO shown in Figure 5. However, Cadence Conformal does redundancy in fixing the flop.

Figure 5: Reset flop changed to set flop in ECO

Cadence Conformal inserts a new set type flop reg1_1 in this ECO. The flop reg1_1 drives the original functional circuit and the old flop reg1 still drives the scan chain fanout reg2. It is not optimal solution and also it causes a new problem. Conformal LEC treats the new flop reg1_1 as not mapped key point. Ant it results in lots of non-equivalent points in equivalence report after ECO.

Figure 6: Cadence Conformal uses inefficient solution to add new set type flop in ECO

Stitch new flops into scan chain

New flops inserted in an ECO should be stitched into existing scan chains to avoid DFT coverage loss. From the industrial data, 100 new non-scan flops in a design with 100K flops can cause more than 0.1% DFT coverage loss. For the high-reliability chips like Automobile IC, the DFT coverage loss is not acceptable. So if there are new flops in a functional ECO, the scan chain should be redone to include the new flops.

Figure 7: Stitch scan chain

GOF provides several ways to insert the new flops into scan chains. The API 'stitch_scan_chain' can be used to automatically stitch scan chains by inserting the new flops. A manually way is supported by using several netlist processing APIs.

Automatic mode to insert flops into a scan chain in the local modules

For example, eight new flops 'state_new_reg_0' to 'state_new_reg_7' are added in fix_design command. To insert them into scan chain in the local module:

Automatic mode to insert flops before one flop

Users can specify one flop instance name, so that GOF can insert all new flops to the scan chain before the flop instance.

For example, insert all new flops to the scan chain before instance 'u_pixel_ctrl/pulse_reg':

Manual mode to connect up all new flops

The scan chain can be re-connected up manually by ECO APIs. And new scan in/out ports are created.

# GofCall ECO script, run_manual_stitch_scan_chain_example.pl
use strict;
undo_eco; # Discard previous ECO operations
setup_eco("eco_manual_stitch_scan_chain_example");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
save_session("current_eco_name"); # Save a session for future restoration
set_error_out(0); # Don't exit if finds error
my @flops = get_cells("-hier", "-nonscan"); # Find all new flops that are not in scan chain yet
# @flops can be defined by reading a list file
if(scalar(@flops)){ # If there are new flops, start the work
  new_port("so1", "-output"); # New a scan out port so1
  new_port("si1", "-input"); # New a scan in port si1
  my $cnt = 0;
  my $now_si;
  foreach my $flop (@flops){
    $cnt++;
    if(is_scan_flop($flop)==0){
      my $flop_name = get_ref($flop);
      my $scanflop = get_scan_flop($flop_name); # If the flop is not scan type, change to scan type flop
      change_gate($flop, $scanflop);
    }
    if($cnt==1){
      change_port("so1", "$flop/Q"); # The first flop drives the new scan out port
    }else{
      change_pin($now_si, "$flop/Q");
    }
    $now_si = "$flop/SI";
    change_pin("$flop/SE", "te"); # All scan enable pin is connected to scan enable signal
  }
  change_pin($now_si, "si1"); # The last flop has the new scan in port driving SI pin
}
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit;