Convert Spare Gate Type

In metal only ECO, the spare gate types are normally INV/AND/NAND/OR/NOR/XOR/XNOR/MUX/Flop. Some ECO may use up one or more types of gates and need to convert overflown types to other spare types. One design may have only INV/MUX/Flop types as spare gates. The synthesis engine has difficulty to directly map the random ECO logic to MUX types only logic. GOF provides a way to map a random ECO logic to MUX only logic.

As shown in Figure 1, AND/OR/XOR can be mapped to MUX by reconnecting the input pins. NAND/NOR/XNOR can be mapped to MUX as well, for example NAND=A?(!B):(1'b1), NOR=A?(1'b1):(!B) and XNOR=A?B:(!B)

Figure 1: Convert AND/OR/XOR spare gates to MUX

GOF does two rounds of spare gates mapping to map the ECO logic to MUX only logic. The initial automatic functional ECO patch is mapped to AND/OR/XOR/MUX types in the first round of spare gates mapping. Then GOF changes the AND/OR/XOR types in the patch to MUX according to Figure above and the patch with MUX only is generated. In the second round of spare gates mapping, LEF/DEF files are read in and spare gates instances with INV/MUX/Flop types are extracted from the netlist. And the MUX only patch has all MUXs mapped to the real physical spare MUX gates.

The flow is shown in Figure 2.

Figure 2: Metal Only ECO Flow with MUX Spare Gates

The detail script for spare gates conversion:

read_library("stdlib.lib");
read_svf("-ref", "reference.svf.txt");       # Optional, must be loaded before read_design, must be in text format\n";
read_svf("-imp", "implementation.svf.txt");  # Optional, must be loaded before read_design, must be in text format\n";
read_design("-imp", "netlist_under_eco.v");
read_design("-ref", "netlist_reference.v");
set_top("chip_top");
fix_design;
report_eco;
# First round of spare gates mapping
set_constraints("-type", "TIELO_X1M,AND2_X0P5M,OR2_X0P5B,XOR2_X0P5M,MX2_X4B,INV_X0P5B");
map_spare_cells(); 
report_eco;
# Convert AND/OR/XOR to MUX
my @cells = get_cells("-new", "-hier");
foreach my $cell (@cells){
  my $ref = get_ref($cell);
  print "Change $cell $ref to mux\n";
  if($ref =~ m/^AND/){
    change_gate($cell, "MX2_X4B", ".A(1'b0),.B(B),.S0(A)");
  }elsif($ref =~ m/^OR/){
    change_gate($cell, "MX2_X4B", ".A(B),.B(1'b1),.S0(A)");
  }elsif($ref =~ m/^XOR/){
    my $inv = new_gate("", "INV_X0P5B", "", "$cell/B"); # invert B input
    change_gate($cell, "MX2_X4B", ".A(B),.B($inv/Y),.S0(A)");
  }
}
report_eco;
# Second round of spare gates mapping
read_lef("$cdir/h40.lef");
read_def("$depth/def/chip_top.def");
get_spare_cells("Spare_*/*_SPARE_GATE*");
map_spare_cells; 
report_spares;
report_eco;
write_verilog("eco_chip_top.v");