A Practical Way to Do Netlist ECO & Debug

Mapping Spare Gates with Constraint

After functional ECO, the ECO patch can be synthesized to map to the spare gates. The spare gates list is combination of two inputs AND/OR/NAND/NOR/INV and flops, MUX being optional.

The synthesis can be constrained to control the spare gates type and number being used. The API set_constraint is to set constraint on spare cells type or spare cells number.

We will show that the optimal spare gates list is all AND/OR/NAND/NOR being in the list. The example is to map AIO222X2 to different combinations of spare gates.

Mapping to AND and NOR

The following ECO script is to map AOI222X2 to AND2X1 and NOR2X1 types.

# LEC script, map_spare_cells_example.pl
use strict;
read_library("art.5nm.lib"); # Read in standard library
read_design('-imp', 'imp_net.v');
change_port("out", "AOI222X2", "", "a,b,c,d,e,f");
set_constraints("-type", "AND2X1,INVX1,NOR2X1"); # Map to AND2X1/NOR2X1/INVX1
map_spare_cells;
write_verilog("mapped_verilog.v");

As shown in Figure 1, 3 AND gates and 2 NOR are mapped in the final circuit.

Figure 1: Map Spare Cells to AND and NOR

Mapping to 1 AND and Multiple NOR

The following ECO script sets constraint to use only one AND.

# LEC script, map_spare_cells_example.pl
use strict;
read_library("art.5nm.lib"); # Read in standard library
read_design('-imp', 'imp_net.v');
change_port("out", "AOI222X2", "", "a,b,c,d,e,f");
set_constraints("-type", "AND2X1,INVX1,NOR2X1");
set_constraints("-num", "and<2"); # Force to have only one 'and' type
map_spare_cells;
write_verilog("mapped_verilog.v");

As shown in Figure 2, 1 AND gates and 4 NOR are mapped in the final circuit. But 4 extra inverts are inserted.

Figure 2: Map Spare Cells to One AND and Multiple NOR

Mapping to NAND only

The following ECO script sets constraint to use only NAND type.

# LEC script, map_spare_cells_example.pl
use strict;
read_library("art.5nm.lib"); # Read in standard library
read_design('-imp', 'imp_net.v');
change_port("out", "AOI222X2", "", "a,b,c,d,e,f");
set_constraints("-type", "INVX1,NAND2X1"); # Map to NAND2X1/INVX1
map_spare_cells;
write_verilog("mapped_verilog.v");

Figure 3: Map Spare Cells to NAND

The Best Constraint

From the above experimental runs, the best constraint is to have spare cells type NAND, OR and NOR.

# LEC script, map_spare_cells_example.pl
use strict;
read_library("art.5nm.lib"); # Read in standard library
read_design('-imp', 'imp_net.v');
change_port("out", "AOI222X2", "", "a,b,c,d,e,f");
set_constraints("-type", "AND2X1,INVX1,NOR2X1,OR2X1"); # Map to AND/OR/NOR
map_spare_cells;
write_verilog("mapped_verilog.v");

As shown in Figure 4, 3 AND, one OR and one NOR are used and no invert is used in this mapping.

Figure 4: Map Spare Cells to NAND

The Conclusion for Spare Gates list

So the conclusion for the optimal spare gates list is, it should have AND/OR/NAND/NOR types spare gates. This will make synthesis work in most efficient way and ECO patch size is the smallest.

Check Metal Only ECO for detail

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