A Practical Way to Do Netlist ECO & Debug

Flip-flop Phase Inverted

In power timing critical designs, Place and Route tool may change some flip-flops' phase by adding inverters in input pin and output pin.

Figure 1: Flip-flop Phase Inverted

API set_mapping_method('-phase') is used to handle these cases.

# GofCall ECO script, run_example_ff_phase_inverted.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
set_mapping_method('-phase'); # Check flop phase during LEC
fix_design;
save_session("current_eco_name"); # Save a session for future restoration
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

Check Flip-flop Phase Inverted in user manual

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