Flip-flop Phase Inverted
In power timing critical designs, Place and Route tool may change some flip-flops' phase by adding inverters in input pin and output pin.
Figure 1: Flip-flop Phase Inverted
API set_mapping_method('-phase') is used to handle these cases.
# GofCall ECO script, run_example_ff_phase_inverted.pluse strict;undo_eco;# Discard previous ECO operationssetup_eco("eco_example");# Setup ECO nameread_library("art.90nm.lib");# Read in standard libraryread_design("-ref", "reference.gv");# Read in Reference Netlistread_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECOset_top("SOC_TOP"); # Set the top to the most top module SOC_TOPset_mapping_method('-phase'); # Check flop phase during LECfix_design;save_session("current_eco_name"); # Save a session for future restorationreport_eco(); # ECO reportcheck_design("-eco");# Check if the ECO causes any issue, like floatingwrite_verilog("eco_verilog.v");# Write out ECO result in Verilogexit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears
Check Flip-flop Phase Inverted in user manual