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GOF / 推荐参考流程

选择目标，替换输入，运行 GOF。

这些脚本覆盖常用的 LEC、ECO 和 Debug 场景。每个示例都保留用途注释，便于复制后按项目修改。

阅读文档 完整用户手册

下面的脚本覆盖常用的 LEC、PreMask/PostMask ECO、RTL 引导 ECO 和 Debug 场景。先选择目标，再替换库、网表、顶层模块和测试约束。

使用前准备#

目标推荐流程主要输出
比较两个网表是否等价Netlist vs Netlist LECLEC 日志与非等价点
可增加或删除标准单元的功能 ECOPreMask ECOECO 报告与修改后网表
只能使用已放置 spare cellsPostMask ECO（spare cells）映射到 spare cells 的网表
使用 metal-configurable ECO cellsPostMask ECO（eco cells）映射到 gate-array cells 的网表
从 RTL 差异生成网表补丁RTL Guided ECORTL 差异对应的网表 ECO
查看网表或定位不等价Debug Flow交互式原理图与调试会话

运行前请确认：

  • 标准单元、SRAM 和模拟宏的 Liberty 文件路径正确。
  • Reference 与 Implementation 网表角色没有颠倒。
  • set_top 使用真实顶层模块名。
  • 扫描输出、scan enable、test mode 等测试约束与设计一致。
  • PostMask 流程中的 DEF、LEF、spare-cell pattern 或 gate-array pattern 与实现数据库一致。

所有示例统一使用下面的运行方式：

示例代码bash
# 保存或修改脚本后运行
gof -run gofeco.pl

一、LEC Flow#

1.1、Netlist vs Netlist LEC Flow#

示例代码perl
# filename: goflec.pl
# run: gof -run goflec.pl

use strict;

set_log_file("goflec.log");

# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");

# read ref. netlist
read_design("-ref", "top_syn.v");

# read imp. netlist
read_design("-imp", "top_pr.v");

# set top module
set_top("top_module_name");

# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);

# Optional: Phase inversion detection is disabled by default.
#set_mapping_method("-phase");

run_lec();

二、ECO Flow#

2.1、PreMask ECO Flow#

示例代码perl
# filename: gofeco.pl
# run: gof -run gofeco.pl

use strict;

set_log_file("gofeco_premask.log");

# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");

# read ref. netlist
read_design("-ref", "top_syn.v");

# read imp. netlist
read_design("-imp", "top_pr.v");

# set top module
set_top("top_module_name");

# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);

# eco
fix_design();

# report and write result
report_eco();
write_verilog("top_pr_eco.v");

2.2、PostMask ECO Flow（spare cells）#

示例代码perl
# filename: gofeco.pl
# run: gof -run gofeco.pl

use strict;

set_log_file("gofeco_postmask.log");

# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");

# read ref. netlist
read_design("-ref", "top_syn.v");

# read imp. netlist
read_design("-imp", "top_pr.v");

# set top module
set_top("top_module_name");

# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);

# premask eco
fix_design();
report_eco();

# postmask eco
read_def("top.def");
get_spare_cells("spr_1/spr_gate*");
map_spare_cells();
report_eco();

# report and write result
write_verilog("top_pr_eco.v");

2.3、PostMask ECO Flow（eco cells）#

示例代码perl
# filename: gofeco.pl
# run: gof -run gofeco.pl

use strict;

set_log_file("gofeco_postmask.log");

# read libraries
read_library("stdcell.lib");
read_library("ecocell.lib"); #<-- this lib contains GFILLs and GACells. If you don't have GFILLs in library, please add them manually first.
read_library("sram.lib");
read_library("analog.lib");

# read ref. netlist
read_design("-ref", "top_syn.v");

# read imp. netlist
read_design("-imp", "top_pr.v"); #<-- include GFILLs

# set top module
set_top("top_module_name");

# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);

# premask eco
fix_design();
report_eco();

# postmask eco
read_lef("tech.lef");
read_lef("stdcell.lef");
read_lef("ecocell.lef");
read_def("top.def");

# G and GFILL are the prefix of the names of gate array cells and gate array fillers. They also may be K* or MG*. it decided by your library.
get_spare_cells("-gate_array", "G*", "-gate_array_filler", "GFILL*");
map_spare_cells();
report_eco();

# report and write result
write_verilog("top_pr_eco.v");

2.4、RTL Guided ECO Flow（without re-synthesis）#

示例代码perl
# filename: gofeco.pl
# run: gof -run gofeco.pl

use strict;

set_log_file("gofeco_rtlguided.log");

read_library("-f", "all_liberty.flist");
# > cat all_liberty.flist
# > -lib stdcell.lib
# > -lib sram.lib
# > -lib analog.lib

set_define("SYN");
set_define("ABC", "1");

read_rtl("-ref", "-f", "rtl_old/rtl.flist");
read_rtl("-imp", "-f", "rtl_new/rtl.flist");

set_top("top");
rtl_compare();

read_design("-imp", "top_syn_old.v"); # read old prelayout netlist
set_top("top");

fix_design();
report_eco();

write_verilog("top_syn_eco.v");

三、Debug Flow#

3.1、单网表Debug Flow#

示例代码perl
# filename: gofdebug.pl
# run: gof -run gofdebug.pl

use strict;

set_log_file("gofdebug.log");

# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");

# read netlist
read_design("top_netlist.v");

# set top module
set_top("top_module_name");

start_gui();

3.2、多网表Debug Flow（LEC或者ECO Fail Debug）#

示例代码perl
# filename: gofdebug.pl
# run: gof -run gofdebug.pl

use strict;

set_log_file("gofdebug.log");

# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");

# read ref. netlist
read_design("-ref", "top_syn.v");

# read imp. netlist
read_design("-imp", "top_pr.v");

# set top module
set_top("top_module_name");

# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);

run_lec(); # or fix_design(); in eco mode
start_gui();

四、生成Formality指导文件Flow#

在ECO脚本或者LEC脚本的最后，加上write_compare_points和write_formality_help_filesAPI。

示例代码perl
# ...
run_lec();

write_compare_points("gof_compare_points.rpt");
write_formality_help_files("fm_20240103");

运行后，在目录下生成fm_20240103_config.tcl，在formality signoff LEC脚本match命令之前加上source -echo -verbose fm_20240103_config.tcl，例如：

示例代码tcl
read_db ...

read_verilog -r -05 { resyn.v }
set_top r:/WORK/top

read_verilog -i -05 { eco.v }
set_top i:/WORK/top

# bypass dft

# source help file from gof
source -echo -verbose fm_20240103.config.tcl

match
verify

需要结合项目输入进一步排查？

请附上 GOF 版本、输入类型、执行命令和日志中的第一条错误。

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