Automatic Standard Cells Metal Only ECO Flow

In Metal Only ECO, the design has completed place and route. Any new gates added should map to spare gates that located in the design. GOF supports Standard Spare Cells and Metal Configurable Gate Array Spare Cells post-mask metal only ECO.

Figure 1: Metal Only ECO

Standard Cells Spare Gates Mapping

GOF uses internal synthesis engine or external synthesis tool to map patch logic to spare gates. The spare gate list requires one or both of the following spare type combinations.

In the Figure 2, the circuit generated by ECO in the left side has random standard cells. The mapping process maps the MUX and flop type gates directly to the spare gates, since they have one to one matching gate in the spare gate list. For the complicated cell type AO32, it has to be synthesized and mapped to 3 AND gates and one NOR gate.

Figure 2: Standard Cells Spare Gates Mapping

Spare Gates Synthesis

A Design Exchange Format file is needed to map new instances to the closest spare gate instances. If DEF file is not loaded, GOF processes the ECO with gates type from the spare list without mapping to the exact spare instances. P&R tool like SOC Encounter maps the new instances in the new netlist to the closest spare gates.

In 'fix_design' command, GOF analyzes the top level module and its sub-modules to isolate the non-equivalent points and optimize the logic cone to find the minimum gate count patch circuit.

External Synthesis Tool for Spare Gates Synthesis

The flow can use external Synthesis Tool as well. The executable synthesis command should be in the search path. The supported Synthesis Tool is RTL Compiler from Cadence and Design Compiler from Synopsys.

GOF writes out the patch in Verilog file and a TCL script for external Synthesis Tool if it's enabled. The TCL script is to constrain the Synthesis Tool to use spare gates only when remapping the gates in the patch file. The Synthesis Tool is run with the Verilog file and TCL script as inputs, and it writes out remapped Verilog patch file which has only spare gate types.

When the spare-only patch file is created, user can pause the flow by '-pause' in 'map_spare_cells' command. User can either modify the patch file manually or tunes up the constraint file to rerun the synthesis for several iterations until the patch netlist meets the requirement. Then press 'n' key to resume the flow.

GOF reads back the spare-only patch file and fits the circuit into Implementation Netlist to fix the logic cones.

When ECO is done, a report can be created and ECO netlist/ECO script can be written out for the back end tool and LEC tool.

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