Simulation library is a file with collection of leaf cell in verilog format. The following is a portion of a simulation library file. 

`timescale 10ps/10ps
module BUFX2 (Y, A);
output Y;
input A;

  buf I0(Y, A);
 

endmodule

module BUFX3 (Y, A);
output Y;
input A;

  buf I0(Y, A);

endmodule
 

module AND2X1 (Y, A, B);
output Y;
input A, B;

  and (Y, A, B);

  endmodule