A Practical Way to Do Netlist ECO & Debug

GVT APIs

Summary

Detail Usage

buffer

ECO command. Buffer high fanout ECO nets

Usage:

buffer($net_names, $buffer_name, $fanout); $net_names: Net names to be buffered. Use "," to separate multiple nets, like "eco1_net1,reset2" $buffer_name: The buffer module name from library, leave it blank to let the tool pick one. It supports repeater case by ",", for example, "INVX1,INVX16" would have 'INVX1' drives 'INVX16' and 'INVX16' drives the fanouts. $fanout: How many fanout to insert a buffer.

Examples:

#1. For every 10 fanout of test_mode, add a buffer, BUFX6 buffer("test_mode", "BUFX6", 10); #2. For every 10 fanout of 'clock', add repeaters, INVX2,INVX16 buffer("clock", "INVX2,INVX16", 10); #3. Let the tool pick a buffer buffer("clock", "", 10);

change_gate

ECO command. Modify an instance in ECO
Two types of usages

Usage1:

change_gate($instance, $new_reference, $pin_mapping); $instance: The instance under ECO. Support hierarchical name, "u_abc/U123" $new_reference: The new reference name which the instance changes to, E.G. 'AND3X1'. If no reference is present, the ECO operation is assumed to change the instance's pin connections. $pin_mapping: Input pins mapping, ".new(old)", E.G. ".A1(A),.B1(B)" if two references have same input pins. The option can be empty

Usage2:

change_gate($instance, $pin_connections); $pin_connections: New pin connections, ".A(n242)". The unspecified pins keeps the original connection. E.G. pin 'B' connection is unchanged.

Examples:

#1. U123 has reference OR3X1 with input pins, A,B,C originally # change U123 to AND3X1, all input pins are the same. change_gate('U123', 'AND3X1', ""); #2. A and B keep the connections, discard C change_gate('U123', 'AND2X1', ""); #3. A keeps the connections, B connects to what the old C connects. And discard old B change_gate('U123', 'AND2X1', ".B(C)"); #4. A,B,C keep the same, and new D pin connects to net n123 change_gate('U123', 'AND4X1', ".D(n123)"); #5. AO21X1 has input pins, A0, A1 and B0 change_gate('U123', 'AO21X1', ".A0(A),.A1(B),.B0(C)"); #6. change U123 A to n123, B to n124, keep C connection. change_gate("U123", ".A(n123),.B(n124)"); #7. Rotating A/B/C connections. change_gate("U123", ".A(B),.B(C),.C(A)");

change_net

ECO command. Change a existing net's driver

Usage:

change_net($net, $gate, $instance, $connections); $net: The net to be ECOed $gate: New leaf gate to drive the net $instance: The instance name of the new gate. Optional, if it is empty, assigned by the tool $connections: The new gate input pins connections. If it is empty, the gate is inserted in the net Supported formats, 1. Very detail ".A(net0),.B(net1),.C(net2)" 2. Connect to the pins in alphabetical sequence "net1,net0,net2" indicating A->net1,B->net0,C->net2 3. Other instance/pin "U408/Y,U409/Y,net2" indicating A->U408/Y,B->U409/Y,C->net2 4. Special character '-' is used to connect up the original connection

Examples:

#1. Drive n123 with BUFX2 driven by n40 change_net("n123", "BUFX2", "", "n40"); #2. Drive n123 with AND2X2 driven by n40 and original n123 driver change_net("n123", "AND2X2", "", "-,n40"); #3. Insert a buffer into n123 change_net("n123", "BUFX2");

change_pin

ECO command. Modify pin connection in ECO
Two types of usages. 

Usage1:

change_pin($pin_name, $net); Change pin's connection to a net $pin_name: In the format of "instance/pin", can be more than one pins separated by ",", "instance1/pinA,instance2/pinB", E.G. "U123/A", "U123/A,U345/B" Hierarchical naming style is supported as well, "u_abc/U123/A" The pins have to be input in this mode. $net: The net name the pin connects to. Hierarchical naming style is supported, "u_abc/net123" When the pin and the net are in different hierarchies, ports are added automatically E.G. # The tool creates 4 ports across the hierarchies to connect the net to the pin. change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/net300"); # The tool gets the net tie to Y pin of U300 and do the the same as the previous example. change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/U300/Y");

Usage2:

my $inst = change_pin($pin_name, $leaf_cell, $new_instance, $connection); Insert a new leaf cell to drive the pin $inst: Return new instance name if new gate is created in the command. $pin_name: In the format of "instance/pin", E.G. U123/A Hierarchical naming is supported, u_abc/U123/A The pin can be output in this mode. The tool gets the net the pin drives, and change the command to change_net($thenet, $leaf_cell, $new_instance, $connection); $leaf_cell: The leaf cell name to drive the $pin_name $new_instance: The instance name for the new inserted leaf cell. The option is optional, the tool assigns one if it's empty If use '.', the instance is added to the same hierarchy as the $pin_name $connection: The pins connection for the new cell. Supported formats, 1. Detail format: ".A(net0),.B(net1),.C(net2)" 2. Simple format: Connect to the pins in alphabetical sequence "net1,net0,net2" 3. Mixed format: "u_abc/U123/Y,.B(net1),net2" 4. Special character '-' is used to connect up the original connection 5. Advanced nesting format: change_pin("U189/A", "AOI21X2", "", "U190/Y,,BUFX6(BUFX6(BUFX6(n412)))");

Note:

All strings should be quoted by ' or " to avoid syntax error or undesired effects. If net or instance name has '\', single quotation has to be used. A instance can have '\' dropped in the name, the tool can automatically decide if '\' is needed in the name.

Examples:

#1. U123 has input pins A,B,C, U234 has input pins A0,A1,B # Change A pin of U123 to net12345 change_pin("U123/A", "net12345"); #2. Change A pin of U123 to $net which is defined in the ECO script. change_pin("U123/B", $net); #3. Change A pin of U123 to net12345 change_pin("U123/A,U234/B", "net12345"); #4. Insert "NAND2X2 eco12345_U0(.A(net1234),.B(net5678));" # to drive U123/A change_pin("U123/A", "NAND2X2", "eco12345_U0", "net1234,net5678"); #5. Same as above, with more detail of pin connections change_pin("U123/A", "NAND2X2", "eco12345_U0", ".A(net1234),.B(net5678)"); #6.Insert a buffer to U123 A pin change_pin("U123/A", "BUFX4", "", "-"); #7. Insert NAND2X1 to drive CK pin and new A connects to the original net change_pin("abc_reg_1_/CK", "NAND2X1", "", ".A(-),.B(1'b1)"); #8. Do hierarchical connection change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/U300/Y"); #9. Nested connection change_pin("qcif/num2/u_spare1/B", "AOI21X2", "eco_inst_on_top1", \ "NAND2X2(gte_344/u_smod/U100/Y, gte_344/n114), gte_343/U111, BUFX6(BUFX6(n105))");

change_port

ECO command. Change an output port's driver, or add gate after input port 

Usage1:

change_port($port, $gate, $instance, $connections); $port: The port under ECO, can be input port or output port $gate: New leaf gate to drive the port if the port is output Or add the gate after input port $instance: The instance name for the new leaf cell, optional, the tool assigns one if it's empty $connections: The new gate input pins connections. If it is empty, the gate is inserted in the net Supported formats, 1. Very detail ".A(net0),.B(net1),.C(net2)" 2. Connect to the pins in alphabetical sequence "net1,net0,net2" indicating A->net1,B->net0,C->net2 3. Other instance/pin "U408/Y,U409/Y,net2" indicating A->U408/Y,B->U409/Y,C->net2 4. Special character '-' is used to connect up the original connection

Usage2:

change_port($port, $inst_pin); $port: The port under ECO, output port $inst_pin: In the format of 'u1234/Y', instance-name/pin-name

Note:

The difference of change_net and change_port command change_net changes all drains of the net. change_port changes only the port driver.

Examples:

#1. Add buffer to output port 'out1' change_port("out1", "BUFX1", "eco_buf0", "-");

check_design

Check if the netlist status, searching for unresolved modules, floating and multi-drivers 

Usage:

check_design(@options); @options: -ignore list: Ignore the issues matching the list, E.G. 'FE_UNCONNECT*,SCAN_*'. -eco: Only check instances/wires having been done ECO. Default check all instances/wires -fixfile filename: Create ECO fix file

Examples:

check_design; check_design('-ignore', 'FE_UNCONNECT*'); check_design('-ignore', 'FE_UNCONNECT*,SCAN_*'); check_design("-eco");

compare_nets

Check equivalence of two nets in the reference and implementation netlist

Usage:

my $result = compare_nets($net0, $net1, @options); $net0: The net in the reference netlist. $net1: The net in the implementation netlist. @options: $result: If 1, they are equal, if 0, they are not equal.

Examples:

#1 Compare reg1/D in the reference and reg1/D in the implementation netlist compare_nets("reg1/D", "reg1/D");

convert_gated_clocks

ECO command. Convert gated clocks to MUX logic

current_design

Set the current top level module

Usage:

current_design($module); $module: Set $module as the current top level module. If the argument is missing, return the current setting ".." set to parent module, "~" set to the most top level module

Note:

It can be reset to the root top module by 'undo_eco'. It is alias command of 'set_top'

current_instance

Set the current instance, alias of 'set_inst'

Usage:

current_instance($instance); $instance: Set $instance as the current instance. If the argument is missing, return the current setting ".." set to parent module, "~" set to the most top level module

Note:

It can be reset to the root top module by 'undo_eco'. It has same effect of 'set_top' and 'current_design'

del_gate

ECO command. Delete gate

Usage:

del_gate($inst); $inst: The instance to be deleted.

del_net

ECO command. Delete net

Usage:

del_net($net); $net: The net to be deleted.

del_port

ECO command. Delete port

Usage:

del_port($port); $port: The port to be deleted.

exist_inst

Check if an instance exists

Usage:

my $ret = exist_inst($inst); $inst: The instance for checking $ret: 1, the instance exists 0, the instance does not exist

exist_wire

Check if a wire exists

Usage:

my $ret = exist_wire($wire); $wire: The wire name for checking $ret: 1: exists 0: not exist

flatten_modules

Flatten hierarchical modules in reference netlist

Usage:

flatten_modules(@module_names); @module_names: List of modules to be flatten

Examples:

flatten_modules("retime_1", "sync_cell_0");

get_cell_info

Get information of a module or instance

Usage:

$data = get_cell_info($module_or_inst, @options); $module_or_inst: The module or instance's name @options: -help: Print this information -conns: Get Connections of the item, only when it's instance -type: Get the item's type information. It can be 'ff','cg,'latch','buf', run 'get_lib_cells -type_info' for all existing type in the current libraries An array is returned if this option is present -libname: Get the library name that the cell is in -area: Get the area of the item -size: Get the size of the item -leakage: Get the leakage of the item -ref: Same as 'get_ref instance' if the item property is instance -context: Get detail library information -attribute attribute_name: Check if the cell has the attribute set. 0 or 1 is returned $data: Returned data, if '-attribute' option is present, $data is 0 or 1 In option is '-conns' case, It is a hash having the following data structure my $module = $hash->{module}; my $instance: $hash->{instance}; foreach my $port (keys %{$hash->{connections}}){ my $net = $hash->{connections}{$port}; } If no option is present, it return the item's property: leaf_instance leaf_module hierarchical_instance hierarchical_module

Examples:

#1. Get area of one leaf cell my $area = get_cell_info("AND2X2", "-area"); #2. Get an attribute of one leaf cell my $is_iso = get_cell_info("ISOX2", "-attribute", "is_isolation_cell");

get_cells

Get all cells in the current module or sub-modules

Usage:

my @cells = get_cells($pattern, @options); $pattern: The pattern matching instance name, '*', 'U*', 'U123' or '/UI_.*_./' It can have path, 'u_clk/*', 'u_abc/u_def/*' @options: -help: Print this information -hier: Or -h, do the command hierarchically -ref ref_pattern: Get cells that has reference matching ref_pattern, E.G. -ref OAI* -type type_pattern: Type_pattern can be 'ff','latch','cg','not' ... run 'get_lib_cells -type_info' for all existing type in the current libraries -type_match type_pattern: Get cells that have one of the types matches the type_pattern -leaf: Only leaf cells -new: Only new created ECO instances -verbose: To print out reference with instance -dotpath: Path delimit is '.' instead of '/' -nobackslash: Remove backslash @cells: Returned array with all instances matched

Examples:

#1. Get all instances in the current module get_cells('*'); #2. Get all instances in the current module get_cells(); #3. Get all instances matching 'U234*' in the current module get_cells('U234*'); #4. Regular expression. Get all instances starting with U and followed by # two characters, like U10, U99 get_cells('/U../'); #5. Get all instances matching *reg_*_ hierarchically get_cells('*reg_*_', '-hier'); #6. Get all instances hierarchically and having reference matching DFF* get_cells('*', '-hier', '-ref', 'DFF*'); #7. Get all instances in 'u_kb' get_cells('u_kb/*');

get_conns

Get connections of net or pin in the top level module, return the leafs and the hierarchical connections

Usage:

@result = get_conns($net_or_pin, @options); $net_or_pin: The net name or pin name that needs to get connections. @options: -pin: Return inst/pin format -driver: Return driver only -load: Return load only -count: Return connections count @result: a two dimension array instance, port_name, pin_or_port, load_or_driver, is_it_a_leaf, @result = ([instance_0, pin_0, 'pin', 'load', 1], ... )

Examples:

#1. Net 'n599' has three connections, instance 'U198' is the driver get_conns("n599"); gte_344 A[14] pin load 0 U198 Y pin driver 1 U94 AN pin load 1 #2. Net 'qcifhbeat' has three connections, it is output port of the current top level module get_conns("qcifhbeat") qcifhbeat port load U80 A pin load 1 qcifhbeat_reg Q pin driver 1 #3. The argument in inst/pin format get_conns("U187/A") U294 A1 pin load 1 U187 A pin load 1 U80 Y pin driver 1 #4. Return connections count get_conns("U187/A", "-count"); 3 #5. Return load only and in pin format get_conns("U187/A", "-pin", "-load"); U294/A1 U187/A

get_coord

Get an instance's coordination

Usage:

my ($x, $y) = get_coord($instance); $instance: Instance name

Examples:

my ($x, $y) = get_coord("xbar/U1234"); # $x=100, $y=200 in um

get_definition

Get instantiation of instance

Usage:

my $line = get_definition($inst); $inst: Instance name. $line: The instantiating line

Examples:

get_definition('U78'); Returns "AND2X1 U78(.A(n1), .B(n2), .Z(n3));"

get_driver

Get the driver of a net or pin

Usage:

@driver = get_driver($point, @options); $point: net name or pin name, 'n12345' or 'U12345/A1' @options: -pin: Return in "inst/pin" format, E.G. "state_reg/Q" Return an array if '-pin' is not present -nonbuf: Trace the drivers until none buffer @driver: The driver in array format, if '-pin' is not present. If the point is floating, @driver is empty, $driver[0]: Driver instance name. It is empty if the driver is port $driver[1]: Driver pin or port name. If the driver is a port, it is the port name $driver[2]: Driver type. It is string "pin" or "port" depending on the driver is port or leaf cell $driver[3]: Driver phase. It is valid when -nonbuf is present, indicating if the driver path is inverted 0: not inverted 1: inverted

Note:

1. If '-pin' is present, return a scalar, $driver = get_driver("n12345", "-pin"); 2. Use 'get_drivers' if there are multiple drivers, the return data has different structure

Examples:

#1. Get driver of a net @driver = get_driver("net12345"); @driver has content of ("U1247", "Y", "pin"); #2. port_abc is input port @driver = get_driver("port_abc"); @driver has content of ("", "port_abc", "port"); #3. Return in instance/pin format $driver = get_driver("net12345", "-pin"); $driver has content of "U1247/Y"

get_drivers

Get the drivers of a net or pin

Usage:

@drivers = get_drivers($point, @options); $point: net name or pin name, 'n12345' or 'U12345/A1' @options: -nonbuf: Trace the drivers until none buffer @drivers: An array of the drivers, if the point is floating, @drivers is empty, if the point has multi-drivers, @drivers has more than one items. For each item in @drivers Index 0: instance, it is empty if the driver is port Index 1: pin or port, if the driver is port, return port Index 2: string "pin" or "port" depending on the driver is port or leaf cell Index 3: indicating drive path inverted or not If 'nonbuf' is present, the last item in @drivers is the non-buffer driver So '$nonbuf = pop @drivers' can get the non-buffer driver

Note:

Use 'get_driver' instead if the net has only one driver and 'nonbuf' option is not used

Examples:

#1. Get drivers of a net @drivers = get_drivers("net12345"); @drivers has content of (["U1247", "Y", "pin"]); #2. 'port_abc' is input port @drivers = get_drivers("port_abc"); @drivers has content of (["", "port_abc", "port"]); #3. Buffers in the path @drivers = get_drivers("state_reg/CK", "-nonbuf"); @drivers has content of ( ["buf_inst0", "Y", "pin"], ["inv_inst1", "Y", "pin"], ["and_inst2", "Y", "pin"] )

get_instance

Get instance in the top level module

Usage:

my $instance = get_instance($pattern, @options); $pattern: Match pattern, can have wildcard "*", if it is empty, it is treated as "*" @options: -module: module name to have its instance name found $instance: Return the first instance matching

Examples:

#1. The fist hierarchical instance matching 'ui_*'. $instance = get_instance("ui_*"); #2. Find the instance name of module 'enet_control' $instance = get_instance("-module", "enet_control");

get_instances

Get all hierarchical instances in the top level module

Usage:

my @instances = get_instances($pattern); $pattern: Match pattern, can have wildcard "*", if it is empty, it is treated as "*" @instances: Array of the hierarchical instances

Examples:

@instances = get_instances("UI_*"); # Any hierarchical instances with UI_ as prefix. @instances = get_instances; # All hierarchical instances.

get_leaf_pin_dir

Get leaf cell pin's direction input/output/inout

Usage:

my $dir = get_leaf_pin_dir("$leaf_name/$pin"); $pin: pin name, E.G. A or B or Y $leaf: Leaf cell name, E.G. NAND2X2 $dir: return direction, input/output/inout

Examples:

my $dir = get_leaf_pin_dir("NAND2X2/A");

get_leafs_count

Get all leaf cells name and count in the top level module, return an array 

Usage:

@leaf_count = get_leafs_count; @leaf_count: Array of leaf name and count ( [leaf0, cnt0], [leaf1, cnt1], ...)

Examples:

@leaf_count = get_leafs_count; foreach my $leaf_point (@leaf_count){ my $leaf_name = $leaf_point->[0]; my $count = $leaf_point->[1]; print "LEAF: $leaf_name has $count cells\n"; }

get_lib_cells

Get leaf gates in libraries 

Usage:

my @cells = get_lib_cells($pattern, @options); @options: -help: This information -char: All cells characterization -type leaf_type: Get leaf gates matching type. Leaf_type can be 'ff', 'latch', 'cg', 'buf', 'not', 'and' ... -type_info: List all types in the current loaded libraries -verbose: If $pattern matches only one lib cell, print the cell lib information $pattern: Library cell name pattern, can have '*'. @cells: Return array with name matching

get_loads

Get loads of net or pin in the top level module, return the leafs connections

Usage:

@result = get_loads($net_or_pin, @options); $net_or_pin: The net name or pin name that needs to get fanouts. @options: -nonbuf: Trace the loads until none buffer -bypbuf: Don't include buffer/inverter in the return array -fanend: Fanout endpoints, flops or ports @result: a two dimension array. Each item has format of 'instance' and 'pin_name', @result = ([instance_0, pin_0], [instance_1, pin_1], ... )

get_logic_cone

Get logic cone of nets or pins

Usage:

$result = get_logic_cone(@InstancePinList, @options); @InstancePinList: Instance/pin and net list. $result: 1, the command fails. 0, the command completed successfully @options: -o file_name: Write output to the file. Default logic_cone.v

Examples:

my @InstPin = ('abc_reg/D', 'n12345'); my $ret = get_logic_cone(@InstPin, '-o', 'MyLogicCone.v'); # The logic cone is written out to verilog file 'MyLogicCone.v'

get_match_nets

Get logic equivalent nets in implementation netlist

Usage:

my @nets = get_match_nets($reference_net); $reference_net: Net name in reference netlist @nets: Equivalent/invert nets in implementation netlist

get_modules

Get all hierarchical modules under current module

Usage:

@modules = get_modules($pattern, @options); $pattern: Match pattern, can have wildcard "*", if it is empty, it is treated as "*" @options: -help: Print this information -hier: Or -h, do the command hierarchically @modules: Modules list, ("module0", "module1", ...)

Examples:

@modules = get_modules("*TM*"); # Any hierarchical modules with TM in the name. @modules = get_modules; # All hierarchical modules. @modules = get_modules("-hier"); # All hierarchical modules and sub-modules under current module.

get_net_of

Get net name connecting to a pin

Usage:

my $net = get_net_of($pin); $pin: The pin of the instance, 'U1234.A1' or 'U1234/A1' $net: The net name connecting to the pin

get_nets

Get nets that matching pattern

Usage:

@nets = get_nets($pattern, @options); $pattern: The net naming pattern, "*" or empty for all nets @options:; -const0: Get all constant zero nets -const1: Get all constant one nets @nets: returned net array.

Examples:

1#. Get all nets. @nets = get_nets("*"); 2#. All nets with 'dbuffer' as prefix @nets = get_nets("dbuffer_*"); 3#. Get constant nets @nets = get_nets("-const0");

get_path

Get current hierarchical path

Usage:

$path = get_path(); $path: The current path

get_pins

Get pins of instance or module

Usage:

@pins = get_pins($name, @options); $name: The instance or module name, it can be hierarchical or leaf @options: -input: Get input pins -output: Get output pins -inout: Get inout pins -clock: Get clock pin, only valid for sequential cell, flop latch and gated-clock-cell -reset: Get reset pin, return "" if it doesn't exist -set: Get set pin, return "" if it doesn't exist -data: Get data pins -attribute attribute: Get pins with the attribute -nextstate_type type: Get pins matching the type which can be 'data', 'load', 'scan_in', 'scan_enable' This option is only valid for sequential cell, flop, latch and gated-clock-cell If no option is present, get all pins @pins: All pins returned, in 'instance/pin' format

Examples:

#1. Get input pins of a hierarchical instance my @pins = get_pins("-input", "u_abc/U123"); Result @pins = ("u_abc/U123/A", "u_abc/U123/B") #2. Get pins of a leaf cell @pins = get_pins("AND2X2"); Result @pins = ("A","B","Y")

get_ports

Get all ports in the current top level module

Usage:

@matching_ports = get_ports($pattern, @options); $pattern: Match pattern, can have wildcard "*". If it is empty, it is treated as "*" @options: -input: Get input ports only -output: Get output ports only -inout: Get inout ports only -bus: Get ports in bus format instead of bit blast. The API returns an array point if this option present The item in the array has format of [port, IsBus, MaxIndex, MinIndex] if IsBus == 1, MaxIndex is the Max Index of the bus, E.G, 7 if the bus is port_a[7:0] if ISBus==0, MaxIndex and MinIndex are not defined If no option is present, get all ports @matching_ports: Return ports matching the pattern and the option specified in the current top level module

Examples:

@ports = get_ports("-input", "dsp2mc_*"); # Get input ports with "dsp2mc_" as prefix @ports = get_ports; # Get all ports

get_ref

Get the reference of the instance, return leaf cell name or hierarchical module name 

Usage:

$reference = get_ref($instance); $instance: Instance name, "U123" $reference: Return reference name, "NAND2X4"

get_resolved

Resolve the relative path to module and leaf item

Usage:

($module, $leaf) = get_resolved($relative_path); $relative_path: Relative path, like "u_abc/u_def/U456" $module: Resolved module name, like "def" $leaf: Resolved leaf name, like U456

Examples:

my ($module, $leaf) = get_resolved("u_abc/u_def/U456"); $module has value "def" $leaf has value "U456"

get_roots

Get root designs name

Usage:

my @rootdesigns = get_roots; @rootdesign: returned root designs name

get_spare_cells

ECO command. Get spare cells

Usage:

get_spare_cells($pattern,@options); $pattern: Spare leaf cell instance pattern, E.G. 'spare_inst*/spare_gate*' Extract spare cells from the database with the pattern The first half before '/' is hierarchical instance pattern, it is '*' for top level The second half after '/' is leaf instance pattern It is ignored if -file option is present @options: -o file_name: Write updated spare cell list to the file, by default, it has name 'spare_cells_scriptname.list' -file spare_list_file: Load in spare cell list file instead of extracting from the database

Examples:

#1. Extract spare cells from the database, matching instances like "SPARE_u0" get_spare_cells("*/SPARE_*"); #2. Matching hierarchical instance "someSpare_*" and leaf instance "spr_gate*" get_spare_cells("someSpare_*/spr_gate*"); #3. Extract spare cells from file "spare_cells_list.txt" get_spare_cells("-file", "spare_cells_list.txt");

Note:

The API has to run on top level, set_top('most_top_module') get_spare_cells("someSpare_*/spr_gate*");

gexit

Exit the GofCall interactive mode

Usage:

gexit;

gprint

Print the message and save to log file

Usage:

gprint($info); $info: The message to be printed.

is_leaf

Check if a module or instance is leaf cell

Usage:

my $leaf = is_leaf($name); $name: The module or instance under check $leaf: 0, it's a hierarchical module, (Or the module is not defined) 1, it's leaf cell. Like, NAND4X8

is_seq

Check if a leaf module is a specific sequential cell

Usage:

my $isseq = is_seq($name, @options); $name: The leaf module under check @options: -help: This information -ff: Check if it's flipflop -latch: Check if it's latch -cg: Check if it's gated clock $isseq: 0, it is not the specific sequential cell 1, it is the specific sequential cell

lv_search

Search instances in LayoutViewer window

Usage:

my $ret = lv_search($pattern, @options); $pattern: The pattern matching instance name, '*', 'u_spare*/U*' @options: -help: Print this information -spare: Unused spare cells only

map_spare_cells

ECO command. Map all new created cells to spare cells

Usage:

map_spare_cells; @options: -help: Print this information. -syn Synthesis_command_line: By default, a built-in Synthesis Engine is used. External Synthesis tool can be picked by this option RTL Compiler and Design Compiler are supported. E.G. "map_spare_cells('-syn', 'rc')" to pick RTL compiler "map_spare_cells('-syn', 'dc_shell')" to pick Design Compiler User can specify more values in the synthesis command E.G. '-rc', "rc -E -use_lic RTL_Compiler_Physical" -lib_header file_name: This option is Valid when '-syn' option is present. To insert the content of file 'file_name' to the header of synthesis tcl script. So that '.lib' file to '.db' conversion can be avoided in Design Compiler case. For example, in Design Compiler case, the file content should have set_search_path [list /project/lib/synopsys_db] set_target_library [list art40_hvt art40_svt] set link_library [list art40_hvt art40_svt] -nofreed: Don't add freed gates for synthesis. -nobuf: Don't insert buffers/repeaters in long wires. -notielow: Don't tie low of the input pins of output floating gates, delete them instead -pause: Pause the tool before apply the patch -exact: Map to the exact name of spare cell, by default the tool picks up a spare cell with the same function, for example, pick up 'INVX2' for 'INVX4'

Note:

A DEF file is needed for mapping to exact spare instances.

Examples:

#1. Map to spare cells and use the built-in Synthesis Engine map_spare_cells; #2. Use extra 'rc' option map_spare_cells('-syn', "rc -E -use_lic RTL_Compiler_Physical") #3. Don't add freed cells for synthesis map_spare_cells('-syn', "rc -E -use_lic RTL_Compiler_Physical", "-nofreed")

new_gate

ECO command. Create new gate

Usage:

@return = new_gate($new_net, $reference, $new_instance, $connections);

Note:

if the command is called in the context of return a scalar, the new created instance name returns. The usage is the same as new_net, except $reference has to be defined, and return back instance if scalar present. Run "help new_net" for detail in the shell "GOF >"

new_net

ECO command. Create a new net

Usage:

@return = new_net($new_net, $reference, $new_instance, $connections); $new_net: The new net to be created, if not defined, the tool assigns one automatically $reference: The leaf gate name to drive the net. $new_instance: The instance name of the new cell, or leave it empty to get automatically assigned. $connections: The new gate input pins connections Supported formats, 1. Detail format: ".A(net0),.B(net1),.C(net2)" 2. Simple format: Connect to the pins in alphabetical sequence "net1,net0,net2" indicating .A(net1),.B(net0),.C(net2) 3. Mixed format: "instance/pin" and net, "U408/Y,U409/Y,net2" indicating A to U408/Y, B to U409/Y and C to net2 4. The "instance/pin" can have sub-instance hierarchy, "u_abc/U408/Y" @return: Have the new created instance and net name. $return[0] : New created instance. $return[1] : New created net.

Note:

Hierarchical path is supported in any net or instance in the command, for instance, new_net('u_abc/net124', ... If the command is called in the context of return a scalar, the new created net name is returned. The new net is assumed to be driven in the path it is created, for instance, new_net('u_abc/eco12345_net124'); eco12345_net124 should be driven in sub-instance u_abc after it is created.

Examples:

#1. NAND2x2 instance name 'U_eco_123' driving new net 'net123' new_net("net123", "NAND2X2", "U_eco_123", ".A(n200),.B(n201)"); #2. INVX2 with instance name 'U_inv' is created in u_abc sub-instance # and the input pin of the new invert is driven by n200 in current top level # port would be created if n200 doesn't drive input port to u_abc new_net("u_abc/net123", "INVX2", "u_abc/U_inv", "n200"); #3. Create a new net "net500" new_net("net500"); #4. Create a new instance with new net tied to output pin, input pin is floating. # $return[0] is new created instance, $return[1] is new created net. @return = new_net("", "INVX2", "", "");

new_port

ECO command. Create a new port for the current top level module

Usage:

new_port($name, @options); $name: Port name @options: -input: New an input port -output: New an output port -inout: New an inout port

Note:

The port name has to be pure words or with bus bit, like, abc[0], abc[1]

Examples:

new_port('prop_control_en', '-input'); # create an input port naming 'prop_control_en' new_port('prop_state[2]', '-output'); # create an output port with bus bit 'prop_state[2]' new_port('prop_state[3]', '-output'); # create an output port with bus bit 'prop_state[3]'

place_gate

ECO command. Place gate position

Usage:

place_gate($inst, $x, $y); $inst: The instance to be placed $x,$y: The coordinate

Note:

This command affects the spare gate mapping of the instance.

Examples:

# A flop is added and placed in some location # In 'map_spare_cells' command, the flop is mapped to a spare flop closest to the location change_pin("U123/A", "DFFX1", "eco_dff_reg", ".D(-),.CK(clock)"); place_gate("eco_dff_reg", 100, 200); # location, 100um, 200um map_spare_cells;

place_port

ECO command. Place port position

Usage:

place_port($port, $x, $y); $port: The port to be placed $x,$y: The coordinate This command has effect on change_port ECO command

pop_top

Pop out the saved top level module from the stack and discard the current setting

Usage:

pop_top;

push_top

Set the current top level module and push the previous setting to stack, pop_top can retrieve it

Usage:

push_top($module); $module: Set the $module as the top level module, push the previous setting to the stack

read_def

Read DEF file

Usage:

my $status = read_def(@files, @options); @files: DEF files @options: -defverbose: Report all DEF parsing warnings and errors $status: If zero, the files are read in successfully if one, failed to read in the files

Examples:

my $status = read_def("soc_top.def"); # Read in soc_top.def my $status = read_def("soc_top1.def", "soc_top2.def"); # Multiple DEF files

read_design

Read verilog netlist

Usage:

my $status = read_design(@files, @options); @files: Verilog netlist files @options: -imp: The netlists are implementation design which are under ECO. Normally they are pre-layout netlists. -pnr: The netlists have gone through Place and Route -ref: The netlists are reference design -Top_1: Read design to create Top_1 tree database -Top_2: Read design to create Top_2 tree database -once: Read the file only once, the file is bypassed if the command is executed again

Note:

If no -imp or -ref option is provided, the netlist is assumed 'implementation' $status: If zero, the file is read in successfully if one, failed in reading the file

Examples:

#1. Read in an implementation netlist file my $status = read_design("-imp", "soc_design_resynthesized.gv"); #2. Read in a reference netlist file my $status = read_design("-ref", "soc_design_released.gv"); #3. Read in two reference netlist files my $status = read_design("-ref", "soc_design_released.gv", "soc_io.gv");

read_file

Read timing violation report file

Usage:

my $status = read_file($file_name, @options); $file_name: file name @options: -format format: accu/pt accu --- Accucore report file. pt --- Prime Time report file $status: If zero, the file is read in successfully if one, failed to read in the file

Examples:

my $status = read_file("soc_primetime_hold.report", "-format", "pt");

Note:

Prime Time timing report file should be generated by report_timing command with these options report_timing -nosplit -path_type full_clock_expanded -delay max/min -input_pins \ -nets -max_paths 10000 -transition_time -capacitance

read_lef

Read LEF file

Usage:

my $status = read_lef(@files); @files: LEF files $status: If zero, the files are read in successfully if one, failed to read in the files

Examples:

my $status = read_lef("soc_top.lef"); # Read in soc_top.lef my $status = read_lef("soc_top.lef", "soc_top1.lef", "soc_top2.lef"); # Read in multiple LEF files

read_library

Read standard library or verilog library files

Usage:

my $status = read_library(@files, @options); @options: -v: Treat the @files as verilog library files -lib: Treat the @files as standard library files -f library_list_file: Load library files from list file, the list file has format of -v verilog_lib0.v -v verilog_lib1.v -lib tsmc40.lib -vmacro: Treat the @files as macro library files which are used as macro cell in ECO @files: Standard library files, or verilog library files

Note:

The three options, '-v' '-lib' and '-vmacro' don't coexist. If the file has .lib extension, '-lib' can be omitted, and it is treated as standard library file. If the file has .v or .vlib extension, '-v' can be omitted, and it is treated as verilog file. $status: If zero, the file is read in successfully if one, failed to read in the file

Examples:

my $status = read_library("arm_40_hvt.lib", "arm_40_io.lib"); my $status = read_library("analog_stub.v", "analog_stub2.vlib"); my $status = read_library("-v", "analog_stub.gv"); my $status = read_library("-vmacro", "macrocell.v"); my $status = read_library("-f", "lib_files.list");

rename_net

ECO command. Rename a net name

Usage:

rename_net($oldname, $newname); $oldname: Old net name $newname: New net name

report_eco

Report ECO

Usage:

report_eco($filename, @options); $filename: Write report to the file name. If $filename is not present, print to screen @options: -help: Print this information -simple: Print in simple format

report_spares

Report Spare cells

Usage:

report_spares;

run

Run GofCall script

Usage:

run($script_name);

Examples:

run("eco2.pl");

run_lec

Run Logic Equivalence Check on Implementation Netlist and Reference Netlist

Usage:

run_lec;

sch

Launch schematic to verify ECO

Usage:

sch(@instances, @options); @instances: Instances or nets in the current module to be displayed on the schematic @options: -set value: Set a value when launch the schematic -to value: To existing schematic -both: Load the item in both implementation and reference netlist

Examples:

sch("U123", "U456", "inst0"); sch("clk") sch("in1", "-set", "1"); sch("in1", "-to", "1"); # No action if schematic 1 doesn't exist

set_auto_fix_floating

ECO setting. Enable automatic fixing floating input ports after fix_modules
By default, it is enabled.

Usage:

set_auto_fix_floating(0); --- Disable automatic fixing floating input ports.

set_bound_opti

Enable or disable boundary optimization check. Enabled by default

Usage:

set_bound_opti($val); $val: 1, enable boundary optimization check. 0, disable.

set_buffer

Set buffer type. The tool automatically picks one if the command is not called

Usage:

set_buffer($buffer); $buffer: Lib cell name for buffer

Examples:

set_buffer("BUFX2");

set_buffer_distance

Set distance limit for inserting buffer

Usage:

set_buffer_distance($distance_val); $distance_val: distance to insert buffer, in um

set_constraints

Set constraints for map_spare_cells command

Usage:

set_constraints(@options); @options:; -type type_constraint : Set spare cell type constraint, type_constraint is a string listing spare cells separated by ',' -num num_constraint : Set spare cell number constraint, num_constraint is a string in format of 'mux<16,nand<18'

Note:

The number constraint only controls the number of spare types to be used. The spare gates set should have 'mux', 'nand/and', 'nor/or' and 'inv' types of leaf cells.

Examples:

#1. Use less than 16 'mux' and less than 18 'nand' spare gates in map_spare_cells set_constraints('-num', 'mux<16,nand<18'); #2. Use NAD2X1 NOR2X1 INVX1 and MUX2X1 as spare type gates set_constraints('-type', 'NAND2X1,NOR2X1,INVX1,MUX2X1');

set_dont_use

Set dont use property on library cells

Usage:

set_dont_use(@cell_list); @cell_list: List of the dont use cells which is not used in automatic ECO. Wild card '*' is supported

Examples:

set_dont_use("INVX30","AND2X24"); set_dont_use("PWR_*");

set_eco_effort

ECO setting. Set ECO effort

Usage:

set_eco_effort($effort); $effort: One of the three choices, high, medium and low. By default, high effort is used

Examples:

#1. Change ECO effort to medium set_eco_effort("medium");

set_equal_net

ECO setting. Set two nets to be equivalent in Reference and Implementation netlists

Usage:

set_equal_net($ref_net, $imp_net); $ref_net: The net in Reference Netlist. It should be the first argument $imp_net: The net in Implementation Netlist. It should be the second argument

Examples:

#1. Net n1024 in Reference is equivalent to n2048 in Implementation set_top('a_module'); set_equal_net('n1024', 'n2048'); se_top('design_top'); fix_design(); #2. Sub-hierarchical net n1024 in Reference is equivalent to n2048 in Implementation set_top('top_module'); set_equal_net('/u_a_module/n1024', '/u_a_module/n2048'); fix_design();

set_exit_on_error

Whether the tool should exit when the script runs into an error

Usage:

set_exit_on_error($error, $bit); $error: Error pattern, wild card support. 'E-001', 'E-*' $bit: 1, Exit on the error, default 0, Don't exit on the error

set_exit_on_warning

Whether the tool should exit when the script runs into a warning

Usage:

set_exit_on_warning($warning, $bit); $warning: Warning pattern, wild card support. 'W-001', 'W-*' $bit: 1, Exit on the warning 0, Don't exit on the warning, default

set_ignore_instance

ECO setting. Set ignored sequential or blackbox instances in ECO

Usage:

set_ignore_instnace(@ignored_instances) @ignored_instances: Instances to be ignored in ECO, accept wild card '*'

Examples:

#1. Ignore instances matching RAND_CNT_reg* in ECO set_top('VIDEO_TOP'); set_ignore_instance('RAND_CNT_reg*'); set_top('DESIGN_TOP'); fix_design(); #2. Ignore instances matching current_state_reg* in instance u_video set_top('DESIGN_TOP'); set_ignore_instance('u_video/current_state_reg*'); fix_design();

set_ignore_network

ECO setting. Set ignore network in ECO

Usage:

set_ignore_network(@ignored_nets, @options) @ignored_nets: Net and its network to be ignored in ECO, accept wild card '*' @options: -help: Print this information -pin: @ignored_nets are in pin format, for example, 'DONT_mux_clk/PIN_Y'

Examples:

#1. Ignore scan_en and scan_in set_ignore_network('scan_en*', 'scan_in*'); #2. Ignore PAD PAD_SCAN_EN's output pin 'core' and its network set_ignore_network('PAD_SCAN_EN/core', '-pin');

set_ignore_output

ECO setting. Set ignore output ports

Usage:

set_ignore_output(@ignored_ports) @ignored_ports: Output ports to be ignored, accept wild card '*'

Examples:

#1. Ignore output ports matching *scan_out* in ECO set_top('design_top'); set_ignore_output('*scan_out*'); set_pin_constant('scan_en', 0); fix_design();

set_inside_mod

Set fix scope inside the current module
If set to 1, the tool only use resource inside the current module to fix the non-eq points.
By default, it is disabled.

Usage:

set_inside_mod($val); $val: 0, disable 1, enable

set_inst

Set the current instance, alias of 'current_instance'

Usage:

set_inst($instance); $instance: Set $instance as the current instance. If the argument is missing, return the current setting ".." set to parent, "~" set to the most top level module

Note:

It can be reset to the root top module by 'undo_eco'. It has same effect of 'set_top' and 'current_design'

set_inv_net

ECO setting. Set two nets to be inverted in Reference and Implementation netlists

Usage:

set_inv_net($ref_net, $imp_net); $ref_net: The net in Reference Netlist. It should be the first argument $imp_net: The net in Implementation Netlist. It should be the second argument

Examples:

#1. Net n1024 in Reference is inverted to Net n2048 in Implementation set_top('VIDEO_TOP'); set_inv_net('n1024', 'n2048'); fix_design();

set_invert

Set invert type. The tool automatically picks one if the command is not called

Usage:

set_invert($invert); $invert: Lib cell name for invert

Examples:

set_invert("INVX2");

set_keep_format

Set keep format of the original verilog when ECO is done

Usage:

set_keep_format($value); $value: 0: disable, 1 : enable.

set_keep_tree

Set keeping buffer tree, so that buffer tree won't be removed in ECO
By default , it is disabled.

Usage:

set_keep_tree($val); $val: 0, disable 1, enable

set_leaf

Set a hierarchical module to be leaf. Useful to stub hierarchical instances

Usage:

set_leaf($module_name, $value); $module_name: The module to be set leaf or not set to leaf $value: 1 or larger than 1, set the module as leaf. 0 not set to leaf. If $value is not present, the default value is 1.

Examples:

set_leaf($module_a); # set $module_a as a leaf set_leaf($module_a, 1); # same as the above set_leaf($module_a, 0); # remove the leaf setting

set_log_file

Set log file name

Usage:

set_log_file($filename); $filename: Log file name

set_mapping_method

LEC setting. Detecting flop phase inversion.

Usage:

set_mapping_method("-phase");

set_max_lines

Set max output lines

Usage:

set_max_lines($num); $num: New max lines number. Default to be 500

set_max_loop

Setup max loop, the tool stops logic optimization when max loop number is reached

Usage:

set_max_loop($value); $value: Setup BDD threshold, default 40000

set_mod2mod

Set reference module mapping to implementation module

Usage:

set_mod2mod($refmod, $impmod); $refmod: The reference module name $impmod: The implementation module name

Note:

The command is used when reference netlist is partial

set_mu

MU configuration, setup MU value for BDD threshold

Usage:

set_mu($value); $value: Setup BDD threshold, default 12000

set_noexact_pin_match

ECO setting. Don't match some special pins
These pins normally don't exist in RTL but added by Synthesis, DFT or other tools.

Usage:

set_noexact_pin_match($pattern); $pattern: Pin pattern in regular expression, '\bIN\d+\b'

Note:

The command only apply to Reference Netlist

Examples:

#1. Don't match pins like IN0, IN1, IN2 set_noexact_pin_match('\bIN\d+\b');

set_phase_adjust_en

Enable phase adjusting

Usage:

set_phase_adjust_en($val); $val: 0, Disable phase adjusting 1, Enable phase adjusting, by default

set_pin_constant

Set pin to a constant value

Usage:

set_pin_constant($pin, $value, @options); $pin: Input pin name. It can be a bus. $value: Decimal value that the pin should be set @options: -help: Print this information -both: Set the pin to the constant value on both Implementation and Reference. Enabled by default. -imp: Set the pin to the constant only on Implementation -ref: Set the pin to the constant only on Reference

Examples:

#1. Set test scan test pin to low set_top('DESING_TOP'); set_pin_constant('PIN_SCAN_TEST', 0); set_ignore_output('PIN_SCAN_SO*'); fix_design(); #2. Set one bus port to all ones on Implementation set_top('DESING_TOP'); set_pin_constant('PIN_CONTROL[3:0]', 15, '-imp'); fix_design();

set_power

Set power pins connections for leaf cell

Usage:

set_power($leaf_cell, $connections); $leaf_cell: Leaf cell name. Like NAND2X4 $connections: Power pins connections, like ".GND(GND),.VDD(VDD)"

set_preserve

Set preserve property on instances. The tool does not remove them in ECO

Usage:

set_preserve(@instances); @instances: Instances to be preserved in the current module Accept wild card '*'

Examples:

set_preserve("u_donttouch0", "u_1000"); set_preserve("DONT*");

set_quiet

Run script in quiet mode

Usage:

set_quiet;

set_recovery_distance

Set distance limit for gates recovery in ECO

Usage:

set_recovery_distance($distance); $distance: Distance to recover deleted gate, in unit of 'um'

set_remove_undsc_in_ref

ECO setting. Remove last '_' in flop instance in Reference Netlist
It's a special command to remove the last '_' in flop instance in Reference Netlist 
   to match Implementation Neltist.

Usage:

set_remove_undsc_in_ref($value); $value: 1, enable. 0, disable

Note:

The command only apply to Reference Netlist

set_tiehi_net

Set tiehi net name, it is used if tiehi net is needed in ECO

Usage:

set_tiehi_net($netname); $netname: Tiehi net name, E.G. '___logic1___'

set_tielo_net

Set tielo net name, it is used if tielo net is needed in ECO

Usage:

set_tielo_net($netname); $netname: Tielo net name,

Examples:

set_tielo_net("___logic0___"); set_tielo_net("TIE_HILO_TIELO_NET");

set_top

Set the current top level module

Usage:

set_top($module); $module: Set $module as the current top level module. If the argument is missing, return the current setting ".." set to parent module, "~" set to the most top level module

Note:

It can be reset to the root top module by 'undo_eco'

set_tree

Set the current tree, if there are more than one sets of databases

Usage:

set_tree($tree); $tree: It can be the default tree 'Top'. Or 'Top_1' if you use -Top_1 option to load in other design Or Top_ref in when using read_design("-ref", reference_netlist) If $tree is not defined, the current database name is returned

Note:

Implementation tree 'Top' has aliases of 'imp', 'IMP' Reference tree 'Top_ref' has aliases of 'ref', 'REF'

Examples:

set_tree("Top"); set_tree("IMP"); # Same as the above set_tree("Top_ref"); # Set to reference tree set_tree("ref"); # Same as the above, set to reference tree set_tree(); # Return the current database name. E.G. 'Top_ref'

set_user_match

Set match between multi-bit flops to multi-bit flops, and between multi-bit flops to single bit flop

Usage:

set_user_match($inst1, $inst2); $inst1: The first flop instance, in the format of 'r:reg_1_0A/\*dff.00.0\*' if it is multibit or 'r:reg_1A' if it is single bit $inst2: The second flop instance, in the format of 'i:reg_1_0A/\*dff.00.0\*' if it is multibit or 'i:reg_1A' if it is single bit

Examples:

set_user_match('r:reg_1_0A/\*dff.00.0\*', 'i:reg_0A'); set_user_match('r:reg_1_0A/\*dff.00.1\*', 'i:reg_1A'); set_user_match('r:reg_2_1A/\*dff.00.1\*', 'i:reg_1_0A/\*dff.00.0\*');

set_verbose

Run script in verbose mode

Usage:

set_verbose;

setup_eco

ECO command. Setup ECO

Usage:

setup_eco($eco_name, @options); $eco_name: ECO name, like eco01234 @options: -help: Print this information. -comments comments: Comments to appear at the beginning of ECO netlist.

Examples:

#1. Setup ECO name setup_eco('eco1234') #2. Setup ECO name with comments setup_eco('eco1234', '-comments', 'Fix abc_state state machine');

source

Run GofCall script

Usage:

source($script_name);

Examples:

source("eco2.pl");

Note:

It has the same behavior as 'run' command

start_gui

Start GUI windows

Usage:

start_gui;

stitch_scan_chain

ECO command. Stitch scan chain

Usage:

stitch_scan_chain(@options); @options: -to $flop_inst: Stitch all new flops into the flop_inst

Note:

The command creates a new sub-scan-chain for the all new flops, break the chain connecting the instance, and stitch in the new sub-scan-chain.

Examples:

stitch_scan_chain("-to", "abc_reg"); # Insert new flops' scan chain into the existing flop 'abc_reg'

suppress_warnings

Suppress warning messages

Usage:

suppress_warnings(@messages) @messages: Warning messages. 'W-001', 'W-002'

swap_inst

ECO command. Swap two instances with same input/output pins.

Usage:

swap_inst($inst1, $inst2); $inst1,$inst2: Swap these two instances.

Note:

$inst1 and $inst2 should have the same input/output pins.

Examples:

swap_inst("spare1/spr_and0", "spare2/spr_and1");

undo_eco

ECO command. Undo eco operations, restore the database to the original state.

Usage:

undo_eco();

write_dcsh

ECO command. Write ECO result in Design Compiler dcsh script format

Usage:

write_dcsh($dc_script_name); $dc_script_name: Synopsys Design Compiler dcsh script name.

Examples:

write_dcsh("eco12345.dcsh");

write_perl

ECO command. Write GofCall ECO script compatible with Perl

Usage:

write_perl($gofcall_script_name); $gofcall_script_name: GofCall ECO script name

Note:

The command can be used after 'fix_logic' API. Detail ECO operations are written out.

write_soce

ECO command. Write ECO result in Cadence SOC Encounter script format

Usage:

write_soce($soc_encounter_script_name); $soc_encounter_script_name: Cadence SOC Encounter script name.

Examples:

write_soce("eco12345.soce");

write_spare_file

ECO command. Write spare cells list to a file

Usage:

write_spare_file($filename); $filename: Spare cells file name to be written out

Note:

Any used spare cell has '#' in the start of the line

write_tcl

ECO command. Write ECO result in Design Compiler tcl script format

Usage:

write_tcl($tcl_script_name); $tcl_script_name: Synopsys Design Compiler tcl script name.

Examples:

write_tcl("eco12345.tcl");

write_verilog

ECO command. Write ECOed netlist to a verilog file

Usage:

write_verilog($verilog_file, @options); @options: -help: Print this information -all: Keep the modules in the netlist file even they are not the sub-modules of the top module $verilog_file: Write verilog file name, should be different from existing netlist file name.

Note:

When the design is read in by multiple netlist files, set_top command should be used to make the correct file saved out

Examples:

#1. The design is read in by 'gof -lib tsmc.lib ethernet_top.v' # After ECO, to write ECO netlist use command write_verilog("ethernet_top_eco.v"); #2. The design is read in by multiple netlist files, # 'gof -lib tsmc.lib mem_control.v dsp.v ethernet_top.v' # The ECO is done on 'mem_control' module, to save the netlist set_top("mem_control"); write_verilog("mem_control_eco.v"); #3. The design is read in by 'gof -lib tsmc.lib ethernet_top.v', # ethernet_top.v has 'mem_control' and 'dsp' sub-modules # The following commands only write 'mem_control' and its sub-modules set_top("mem_control"); write_verilog("ethernet_top_eco.v"); #4. The design is read in by 'gof -lib tsmc.lib ethernet_top.v'. # ethernet_top.v has 'mem_control' and 'dsp' sub-modules # The following commands write all modules in ehternet_top.v set_top("mem_control"); write_verilog("ethernet_top_eco.v", "-all"); #5. The design is read in by 'gof -lib tsmc.lib ethernet_top.v'. # ethernet_top.v has 'mem_control' and 'dsp' sub-modules # The following commands write all modules in ethernet_top.v set_top("ethernet_top"); write_verilog("ethernet_top_eco.v");

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