NanDigits Design Automation

More powerful partial schematic. nECO can't move cell's position, while GOF can readjust cells position and connections after schematic is drawn so that all items involving in ECO are close to each other.

Q: What about Encounter Conformal ECO Designer then?
- Conformal ECO has trouble to handle hierarchical netlist.
- Conformal ECO does bad job if flip-flops involved.
- It's expensive and it's overkill for most ECO cases
- One design flow model makes it inconvenient
  - Design company outsourcing to back-end vendor
  - The back-end vendor inserts scan/bist/clock-tree
  - A lot of iterations between design and back-end
  - It consumes too much time to create another set of re-synthesized reference netlist
  - Modify the gate-level netlist directly is the optimal solution
  - GOF fits in the modification perfectly
- GOF can do one gate ECO up to thousands gates logic cone ECO
- GOF has provide a programming interface
Q: Can GOF do thousands gates ECO?

Yes, GOF can replace a Logic Cone in one netlist by the Logic Cone in another netlist. It's very useful when RTL code has big changes in one state machine generation. Resynthesis has to be done. GOF can figure out the new Logic Cone driving the state machine and replace the old netlist's Logic Cone by new one. GOF is doing ECO Compiler's job in this case. Check Logic Cone ECO for detail.

GOF has perl compatible script interface for ECO or netlist processing. Check GofCall for detail.

Q: I have a bunch of files with extension of .v and .vlib in a library directory, how to load them as library files?

gof +libext+.v+.vlib -y the_library_directory -v the_other_library_file.vlib netlist.v Or check Usage for detail.

Unlimited size, as long as the machine has enough memory and CPU can access. 500M bytes netlist normally uses 1.0G to 1.8G memory space.

Q: Why not manually edit the netlist by Emacs or VI?
- It was doable for small size digital design.
- Moore's law is against you.
- Adding ports is big headache.
- GOF can do hierarchical ECO which adds ports automatically.
Q: What is Timing ECO? How is GOF used in Timing ECO?

In netlist timing closure period, ASIC designers have to do a lot of timing ECOs according to timing violations report file.
Timing ECO process is to fix setup or hold timing violations without changing RTL functions.
It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time.
Making things more complicated is a lot of paths have a lot shared cells in sub-paths.
Handle timing ECO efficiently.

Parse synopsys PrimeTime timing violation report file.
Summary path violations and bottlenecks.
And feed violated paths into GOF ECO flow automatically.
Users have very clear view of the violated path connectivity and relation with other paths in a schematic.
Check one example of Timing ECO.